how the output of flip flop is determine by the input (truth table)

[Parth86]

I understand the truth table for gates but i am having trouble to understand the concept of flip flop. how the output of flip flop is determine by the input
for example D flip flop I want to make truth table for D flip flop d flip flop has two input D and clk and two output Q and Q- how to make truth table and when we use set reset input please explain anyone

 

[MikeMl]

The table must contain two groups of columns: Present State and Next State

If you consider that Qbar is always just NOT Q, you can leave it out of the table.

If you consider just D, Clk and Qn, then there are 2^3=8 possible Present State combinations, so your table will have eight rows, with three columns: D, Clk and Qn.

The Next State will have just one column, Qn+1.

 

[MikeMl]

Present | Next
 State  | State
--------|------
D Clk Qn| Qn+1
--------|------
0  0  0 |  0
0  0  1 |  1
0  1  0 |  0
0  1  1 |  0
1  0  0 |  0
1  0  1 |  1
1  1  0 |  1
1  1  1 |  1

You interpet Clk=1 as a clock event (whatever that is; rising edge, falling edge?) happened, and Clk=0 as no clock happened.

I'll let you post the expanded table including asynchronous Set and Clr

 

[Parth86]

Present | Next
State  | State
--------|------
D Clk Qn| Qn+1
--------|------
0  0  0 |  0
0  0  1 |  1
0  1  0 |  0
0  1  1 |  0
1  0  0 |  0
1  0  1 |  1
1  1  0 |  1
1  1  1 |  1

You interpet Clk=1 as a clock event (whatever that is; rising edge, falling edge?) happened, and Clk=0 as no clock happened.

I'll let you post the expanded table including asynchronous Set and Clr

I know about input d and clk but i don't know about Qn and Qn+1 in table when it become high and low how to know

 

[rumpfy]

I suggest you get the data sheet for a 7474 IC(dual D flip flop), and then ask specific questions about that device. Philips have a HC/HCT74 mos type. There are other D flip fops too.

 

[MikeMl]

I know about input d and clk but i don't know about Qn and Qn+1 in table when it become high and low how to know

Well, since you made no attempt to understand the truth table of the D flop I posted above, let me try to put it in words:

Regardless of what the state of Q is now, after a Clk, the state of Q will become whatever the value of D was just as the Clk happened. If no Clk happens, then the state of Q will be retained as long as the Flop is powered.

See if you can prove that the truth table I posted does this...

 

[crutschow]

As the old saying goes, you can lead a horse to water but you can't make him drink.

 

[Parth86]

Well, since you made no attempt to understand the truth table of the D flop I posted above, let me try to put it in words:

Regardless of what the state of Q is now, after a Clk, the state of Q will become whatever the value of D was just as the Clk happened. If no Clk happens, then the state of Q will be retained as long as the Flop is powered.

See if you can prove that the truth table I posted does this...

if clock happened means clock=1
then output will be same as input D

--------------
D Clk |Qn
--------------
0 1 | 0
1 1 | 1

If no Clk happens, then the state of Q will be retained
D Clk |Qn
--------------
0 0 | 0
1 0 | 0

 

[MikeMl]

But you left out half the states. There are eight of them; not four.

 

[crutschow]

To clarify "Clk happens" means at the instant the clock changes state (typically low to high). The D input has no effect otherwise.

 

[Parth86]

But you left out half the states. There are eight of them; not four.

But you left out half the states. There are eight of them; not four.

Present | Next
State | State
--------|------
D Clk Qn| Qn+1
--------|------
0 0 0 | 0
0 0 1 | 1
0 1 0 | 0 if clock =1 then output will be same as input d so Qn=0
0 1 1 | 0 here clock =1 then why output will be Qn=1
1 0 0 | 0
1 0 1 | 1
1 1 0 | 1
1 1 1 | 1

clear my confusion

Present | Next
State | State
--------|------
D Clk Qn| Qn+1
--------|------
0 1 0 | 0 if clock =1 high then output will be same as input d so Qn=0
0 1 1 | 0 here clock =1 then why output will be Qn=1 it should be same as above

 

[crutschow]

Read my post #10. It's not the state of the clock. The clock is edge triggered. The FF only changes state at the clock edge. It has no effect otherwise.

 

[Parth86]

If no Clk happens, then the state of Q will be retained

what does it mean can you explain with small example

 

[crutschow]

If no Clk happens, then the state of Q will be retained

what does it mean can you explain with small example

Suppose that during the last low-to-high Clk transition the D input was high, generating a high on the Q output. Now if the D value changes to low the FF Q output will still stay high until the next low-to-high Clk transition. As long as there's no clock transition the output state stays unchanged no matter what the state of the D input. In other words the FF has memory.

 

[ronsimpson]

In the table below the bottom three states have to do with Set and Reset.
If there are no S and R then the table can be made very simple.

The Q and /Q are unaffected by the state of Data or Reset.
No matter what state D and C are in, the Q value holds.
Dats=x, Cloack=x, Q=Q (/Q= not Q)

Only on the rising edge of Clock , D appear on Q.
On ^C D->Q
So the top two lines can be written as one line.

I only see two lines. (assuming no S & R)
Q=Q
^C causes D->Q.

 

[Parth86]

i am trying to understand below table
_/ = clock raising from low to high
| = clock is high
_ = clock is low

Present | Next
State | State
--------|------
clk D Clk Qn
--------|------
_ 0 0 0
_ 0 0 1
_/ 0 1 0 when clock raising low to high Qn will be same as D
| 0 1 1
_ 1 0 0
_ 1 0 1
_/ 1 1 0 when clock raising low to high Qn will be same as D
| 1 1 1


according to crutschow if the D value changes to low the FF Q output will still stay high until the next low-to-high Clk transition. but this table is not following above statement

please explain this table in this way ( clock raising , clock low, clock high)

 

[ronsimpson]

according to crutschow if the D value changes to low the FF Q output will still stay high until the next low-to-high Clk transition. but this table is not following above statement

The only tine Q can change is when C has a _/ . All other states of C and D have no function.
------------------------------------------------------------
This may sound confusing:
If D=1 and Q=1 (or if D=0 and Q=0) Then C _/ also has no function.
....That is to say if D=Q then C _/ has no function.

The only time some thing happens is when D=/Q and C_/.
......D=/Q (D not equal to Q) C_/ (rising edge)

 

[Parth86]

All other states of C and D have no function.


so how can find out the value of Qn and i also want to ask the table given by MikeMl is true or not

 

[ronsimpson]

I don't like MileMi's table, partly because he said "Clk=1 as a clock event". I think C=0 means low. I think C=1 means high. We need a symbol for clock event. (^) or (_/)
I say C=0, nothing will change. No function. or The function is to store (hole) the value of Q.
.........C=1, nothing will change. No function.
.........C=_/ rising edge, The value of D is now stored on Q.
I think you can not have a table of 1s and 0s because the part has no function for 1 or 0. All combinations of 1s and 0s all result in Q=? (to be more curate Q=Q, or Q does not change, we don't know what it is but it does not change)

We can not know what Q is until we have a rising edge of C and we know what D is at that time. Now we know know Q.

so how can find out the value of Qn and i also want to ask the table given by MikeMl is true or not

If by Qn you mean Q after the clock rising edge: than Qn=D

 

[Parth86]

I don't like MileMi's table, partly because he said "Clk=1 as a clock event". I think C=0 means low. I think C=1 means high. We need a symbol for clock event. (^) or (_/)
I say C=0, nothing will change. No function. or The function is to store (hole) the value of Q.
.........C=1, nothing will change. No function.
.........C=_/ rising edge, The value of D is now stored on Q.
I think you can not have a table of 1s and 0s because the part has no function for 1 or 0. All combinations of 1s and 0s all result in Q=? (to be more curate Q=Q, or Q does not change, we don't know what it is but it does not change)

We can not know what Q is until we have a rising edge of C and we know what D is at that time. Now we know know Q.

If by Qn you mean Q after the clock rising edge: than Qn=D

now I understood if clock is raising from low to high the value of d is stored in Qn
but you said c=0 nothing will change no function
c= 1 nothing will change no function

D Clk |Qn
--------------
0 0 | 0 c=0 nothing will change no function what will be the value of Qn
1 0 | ? c=0 nothing will change no function what will be the value of Qn
0 1 | 0 clock rising edge: than Qn=D
1 1 |? c=1 nothing will change no function what will be the value of Qn


what does it mean that nothing will change no function