Dear guys,
I would like to design a HEX to Seven Segment Decoder using K-maps for seven 4-input functions.
eg 0000 produces 0 while 1111 produces F
I use kMap to derive the logic function for a,b,c,d,e,f,g segment
This is what I get
a = BC + A'C + AD' + B'D' + A'BD
b = B'D' + B'C' + A'CD + AC'D + A' C' D'
c = C'D + A'D + AB' + A'B + B'C'
....
g = AC + B'C + AB' + BC'D + A'BD'
As you can notice, if I draw out the logic diagram, it will be complex. eg: Just a alone, I will need 5 AND gates and 5 inputs OR gates.
Are there any ways I can minimize the use of my logic gates?
Thank you
I would like to design a HEX to Seven Segment Decoder using K-maps for seven 4-input functions.
eg 0000 produces 0 while 1111 produces F
I use kMap to derive the logic function for a,b,c,d,e,f,g segment
This is what I get
a = BC + A'C + AD' + B'D' + A'BD
b = B'D' + B'C' + A'CD + AC'D + A' C' D'
c = C'D + A'D + AB' + A'B + B'C'
....
g = AC + B'C + AB' + BC'D + A'BD'
As you can notice, if I draw out the logic diagram, it will be complex. eg: Just a alone, I will need 5 AND gates and 5 inputs OR gates.
Are there any ways I can minimize the use of my logic gates?
Thank you