originally, a frequency counter consisted of a series of cascaded BCD counters and a timed gate. when the gate was high, the input signal caused the counters to count, when the gate momentarily went low (once per second, triggered by the transition), the count on the counters would be transferred to a display latch, and the counters would be reset for the next count. the gate goes high again, and the new count begins, while the latched data is displayed on a row of 7-segment LED digits. for best accuracy, the gate timing should be controlled from a very accurate timebase, usually a 10Mhz crystal divided down to 1hz by a series of cascaded decade counters. all this can be done with standard TTL or CMOS logic.