Help with addressable latch (or logic ICs in general)

[core]

In short, I have two input pins of an IC connected together which appear to somehow change states at slightly different times, resetting the chip.

The chip is a 74HCT259 addressable latch, and the two pins in question are -LE- and -MR-. In my circuit, they are usually both at high, until a momentary switch is pressed, when of course they go low for as long as the switch is held. Now understand that these two pins are jumpered together! The problem is that when the switch is released and +5V is sent to both pins, the LE seems to "realize" the new state before MR, resulting in a complete reset of the chip (and therefore a useless circuit).

How can this be? Does this chip not allow such simultaneous operation of those two pins? My logic levels are good (coming from an RTL NOR gate), and I'm not mixing in analog or anything like that. The three address bits and the data pin are all jumpered high for testing, so that's not an issue. The switch is _not_ debounced (yet), but in this particular case I don't see why that would matter.

Weeks ago I did manage to get it working fine by using a crude kludgy mess of a couple resistors, a capacitor, and diode on the LE pin, causing a slight delay while the capacitor charged. But today by accident I realized it was acting as a voltage divider and the level on that pin was waaaay off... 'twas a miracle it ever worked at all. (Obviously I'm not an expert on such things.)

What I'm going to do next is string together a bunch of invertors to take advantage of propagation delay, which I'm confident will "work". But surely this is complete overkill for something so simple? How do most folks use latches like this? It just seems hard to believe that I need a whole board full of external components to get the latch to do what it was designed to do.

Thanks in advance,
-core

 

[bonxer]

Two things: Yes, debouncing matters. It doesn't matter how fast or hard you press your switch or button, there is bounce, and it switches between on and off dozens of times.

Also, you say that you do not want the latch to reset. So why to you have the switch connected to the /MR (master reset) ? It seems like it is functioning like it should. You flip the switch, the master reset does what its name famously implies. Perhaps you should connect your switch only to the latch enable. If you still wish to have master reset functionality, connect a separate switch entirely to it. That way you have a latch control, and you have a reset control. Then there are no timing issues involved, and no accidental resets (unless you accidentally hit the wrong switch).

As for why one pin is seeing the signal before the other, though they are getting the signal from the same wire, I don't know right off hand. Perhaps the data sheet mentions something about its order of preference for handling signals. But just holding the /MR high with a pullup resistor should fix the problem anyway, since you don't want it to reset.

 

[core]

Two things: Yes, debouncing matters. It doesn't matter how fast or hard you press your switch or button, there is bounce, and it switches between on and off dozens of times.

Yes, which is actually fine with me. In this particular application, even manually pressing it dozens of times is ok and does not affect operation.

Also, you say that you do not want the latch to reset. So why to you have the switch connected to the /MR (master reset) ?

Because the operation table is as follows:

MR=H LE=H Do nothing, preserve last state
MR=L LE=L Demultiplex (what I want)
MR=H LE=L Addressible latch (I don't want this)
MR=L LE = H Reset chip

So you see, I absolutely have to pull down MR _and_ LE in order to get it into that mode. If I only manipulated latch enable, I'd have to dial up the previous address that was active, set data to zero, hit LE, dial up new address, set data to 1, hit LE again, etc.


Just for a bit of background, the project is a 32 camera multiplexer. On the remote control, one holds down 3 bits representing cam 0-7 then presses one of four bank select buttons. It's those bank select buttons that send MR and LE low, telling the chip to latch onto the appropriate camera and stay there. Of course one has to hold those 3 bits with one's fingers until MR and LE go back high, which is ok with me. Everything does work beautifully with that kludgy RC circuit on the one pin. But the voltage is so low I _really_ need to do it "right" before soldering everything down forever.

 

[ljcox]

I'm not sure I understand what you are trying to do so I'll explain what I think you mean.

1. select the address and hold D high.

2. reset all outputs

3. latch the addressed output high when the switch is released and remains high. All other outputs are to be low.

If this is what you want, then you need to force the MR/LE states through the correct sequence.

As far as I can gather, when you connected the capacitor and diode, this delayed the LE signal and that circuit worked as you wanted.

So when the button was pressed, MR = LE = Low. When released, it passed through the MR = H, LE = L state and finished in the MR = LE = H state.

If this is true, then it passed through the "addressable latch" state and then to the memory state.

So you want a circuit that generates this sequence. The attachment has 2 delays. R1 C1 to suppress bounce (about 100 ms) and R2 C2 to delay the LE signal by about 100 us.

Len

 

[teslatower]

If this is true, then it passed through the "addressable latch" state and then to the memory state.

So you want a circuit that generates this sequence. The attachment has 2 delays. R1 C1 to suppress bounce (about 100 ms) and R2 C2 to delay the LE signal by about 100 us.

Thanks for the response Len! Yes, this exact sequence you describe is what will work. Thanks for the schematic, you're a llifesaver! I'll be building this first thing in the morning after I visit Radio Shack for some NPN transistors that I'll need for those invertors. I'll let you know how it works out!

 

[ljcox]

If this is true, then it passed through the "addressable latch" state and then to the memory state.

So you want a circuit that generates this sequence. The attachment has 2 delays. R1 C1 to suppress bounce (about 100 ms) and R2 C2 to delay the LE signal by about 100 us.

Thanks for the response Len! Yes, this exact sequence you describe is what will work. Thanks for the schematic, you're a llifesaver! I'll be building this first thing in the morning after I visit Radio Shack for some NPN transistors that I'll need for those invertors. I'll let you know how it works out!

The inverters are 74HC14 Schmitt Trigger ICs. Transistor inverters won't work.

However, before you rush off to the Radio Shack, I have thought further about your requirements.

If I understand what you want, I believe you could have used a less complex decoder such as the 74HC42, the 74HC138 or the 16 line 74HC154.

These do not have a latch function, but I don't think you need the latch function. If so, then you don't need the sequencing circuit I posted earlier. However, they have active low outputs, so this may be a disadvantage.

Len

PS I thought you were in Des Moines, not EL paso