help please

[ukrsezer]

hello i have investigation work about 4 cells of 1 bit CMOS SRAM(static random access memory) if you have document about please can you share with me?

 

[ericgibbs]

hello i have investigation work about 4 cells of 1 bit CMOS SRAM(static random access memory) if you have document about please can you share with me?

Look here:

File:SRAM Cell (6 Transistors).svg - Wikipedia, the free encyclopedia

 

[ukrsezer]

Look here:

File:SRAM Cell (6 Transistors).svg - Wikipedia, the free encyclopedia

thanks eric for information
do u know about pspice simulation for 4 cells of 1 bit cmos sram
actually l wrote it in pspice but l have problem in bias point
(
Vcc 6 4 DC 5V
Vi1 0 1 DC 5V
Vi2 0 2 DC 5V
R 0 7 20K
M1 4 5 3 0 lt
M2 4 3 5 0 lt
M3 3 5 6 0 at
M4 5 3 6 0 at
M5 3 2 1 0 at
M6 5 2 7 0 at
.model lt nmos (Kp=1e-4,Vto=-2.5,lambda=1e-5,Cbd=3e-12,Cbs=3e-12,Cgso=4e-7,Cgdo=6e-9,Cgso=6e-9)
.model at pmos (Kp=1e-4,Vto=2.5,lambda=1e-5,Cbd=3e-12,Cbs=3e-12,Cgso=4e-7,Cgdo=6e-9,Cgso=6e-9)
.tran/op 0.01n 25n
.probe )
can u help me ?