LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8004 requires
careful attention to board layout and component selection.
Table I shows the recommended component values for the
AD8004 and Figures 14–16 show the layout for the AD8004
evaluation boards (14-lead DIP and SOIC). Proper RF design
techniques and low parasitic component selection are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 13). One end should be connected to the ground plane and
the other within 1/8" of each power pin. An additional (4.7 μF to
10 μF) tantalum electrolytic capacitor should be connected in
parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on the plot of Figure 10.
Stripline design techniques should be used for long signal traces
(greater than about 1"). These should be designed with the
proper system characteristic impedance and be properly terminated
at each end.