Help needed plzzz..threshold detector

[spatan]

Hi,
I have to design a threshold detector which exactly detects the midpoint of my power supplies which is between 3.3V to 0V. This circuit should be able to give me a low only when it detects 1.65V and when the input voltage is anything apart from 1.65V it should give me a logic High. Now the problem is I have looked at analog comparators, sense amps etc. All these circuits give me a one logic level below 1.65 and another logic level above 1.65. But as you can see that is not what i want. I am at a total loss. Can someone help me plz?

Thank you!!!!!

 

[ljcox]

What you want is a window detector.

This is two threshold detectors - one set at say 1.64 Volt and the other set at 1.66 Volt and their outputs connected in the "wired OR" configuration so that you obtain a Low when the voltage is between 1.64 and 1.66 and a High otherwise.

A small amount of hystersis would be useful to ensure fast transitions.

Len

 

[spatan]

Thank you...help needed again

Thanks a lot for your quick reply. About this window comparator, is there a good book or any links that I can refer to? I just put a google search and am trying to read about it but i thought I would ask you just incase you know any good references . Thanks again!!!! Appreciate your help.

 

[ljcox]

Have you tried www.discovercircuits.com ?

You could also search this forum for "threshold detectors"

Also, look at the dta sheet of the LM 3914 Dot/Bar Display Driver. This is a multi level threshold detector.

If you need more assistance, just ask

Len

 

[spatan]

need a cmos transistor level circuit to design

Wow!!! That was a really quick reply. I am alwayz amazed by how quicky I get answers here . So thanks again and yes I did try disovercircuits.com. Actually I need a mos transistor level implementation circuit. That is why I started with my books but unfortunately they don't have a lot of information either. I use books like Holberg, Razavi, Baker Li Boyce, John Martin etc for analog CMOS and these like I said dont have much info on window comparator. But I will look in this forum to see what I can find.

Thank you.

 

[spatan]

One more question!!!!

Hi Len,
By now I must be sounding pretty dumb. But here is what i understood from the circuits. I have to design two comparators which detect the 2 said reference voltage levels and then have their o/ps in a wired or connection to give me an active low. Right? But here is another question. If I design between 1.64V and 1.66V window then how will i get the intended accuracy of detecting exactly 1.65V. Also I would need rail to rail o/p voltages. Do you think I can use an inverter at the output?

 

[Nigel Goodwin]

Re: One more question!!!!

If I design between 1.64V and 1.66V window then how will i get the intended accuracy of detecting exactly 1.65V.

There's no such thing as 'exactly 1.65V' in the real world, and you shouldn't attempt to specify it as such. You should specify something like '1.65V +/-2%' or '1.65V +/-0.1V' - bearing in mind that the tighter the requirement, the more expensive it's going to be (getting rapidly more so, as requirements increase).

On the same theme, the components you are likely to use are going to be probably 5% tolerance, with 1% probably as good as you can buy. You also have the problem of setting it up, your meter isn't likely to be within 1% tolerance.

Is this for an actual application?, or is it a homework question?.

 

[ljcox]

Re: need a cmos transistor level circuit to design

Wow!!! That was a really quick reply. I am alwayz amazed by how quicky I get answers here . So thanks again and yes I did try disovercircuits.com. Actually I need a mos transistor level implementation circuit. That is why I started with my books but unfortunately they don't have a lot of information either. I use books like Holberg, Razavi, Baker Li Boyce, John Martin etc for analog CMOS and these like I said dont have much info on window comparator. But I will look in this forum to see what I can find.

Thank you.

Q1. Yes that is right. An alternative to the "wired OR" would be to use a CMOS AND or XOR gate. That will also solve your "rail to rail" issue.

Q2. Nigel's point is very valid. It is not possible to design for exactly 1.65 Volt. It does not matter how much money you spend, you can only design a window detector for a specific range.

Q3. Yes you can use an inverter if you wish, but it may not be necessary since you should be able to obtain the correct level from the window detector (ie. active low)

Len

 

[spatan]

Hi!!!!! comparator circuits

Hi Len and Nigel,
This is actually a project where I have to design a dual slope ADC in 0.35 CMOS technology. I have to simulate the transistor level circuits like a switched capacitor integrator, comparator etc and then layout the whole chip. That is why I have been asking for specific ciruits not using any ICs.
For the two comparators can I just go ahead and use a two stage openloop op amp comparator? What about regenerative comparators? I am thinking I cannot use tham as they are biased exactly at mid point. Are there any other comparator circuits that you can suggest. I need them to work pretty fast like respond within 30ns.
Thanks a lot again!!!!!!

Sumera

 

[ljcox]

Sumera,
If I understand your post, you are intending to design an IC comparitor.

I don't know where you would find a comparitor circuit that will operate that fast. If you used op amps, they would need a very high slew rate.

You could design a Schmitt Trigger (sometimes called Emitter Coupled Binary) circuit using either bipolar transistors or FETs.

I don't know what you mean by a "regenerative comparitor", I assume it is one with positive feedback in order to provide hystersis.

You said "I am thinking I cannot use them as they are biased exactly at mid point" I don't understand this point.

Len

 

[spatan]

claryfying things!!!

Hi Len,
I am sorry I cudnt make myself clear. What I meant by I cannot use comparators that are biased exactly at midpoint is because I want active lows only at 1.65 and not above or below it.
But regenerative comparators i.e positive feedback comparators don't give that kind of an action as they pull the o/p to rails once they recognize an i/p below the bias point of 1.65volts.
So if I am designing a transistor level analog CMOS circuit , then are you telling me that I cannot design a window comparator to work at a speed of 30ns?

Thanks for all your help!!!

Sumera

 

[spatan]

one more thing!!!!!

Hi,
I had spoken to my professor today and he said a window comparator might not work as it is designed for large windows and to get a window of only 20mv ie, between 1.64V and 1.66V might not be possible. Is this true? If it is then I am back to square one!!!!!! What do you think?

Thank you,
Sumera

 

[Nigel Goodwin]

Re: one more thing!!!!!

Hi,
I had spoken to my professor today and he said a window comparator might not work as it is designed for large windows and to get a window of only 20mv ie, between 1.64V and 1.66V might not be possible. Is this true? If it is then I am back to square one!!!!!! What do you think?

Window comparators can be designed for any window you need - but your quoted requirement is under 1%, this will obviously cause problems with anything you might design - under 1% is a pretty tight tolerance and will cost a lot of money to achieve in a repeatable commercial design.

 

[ljcox]

Re: one more thing!!!!!

Hi,
I had spoken to my professor today and he said a window comparator might not work as it is designed for large windows and to get a window of only 20mv ie, between 1.64V and 1.66V might not be possible. Is this true? If it is then I am back to square one!!!!!! What do you think?

Thank you,
Sumera

I agree with Nigel's comments. So you may have to make the window wider. Besides, I don't see why you need such a narrow tolerance.

Len

 

[ljcox]

Re: claryfying things!!!

Hi Len,
1. I am sorry I cudnt make myself clear. What I meant by I cannot use comparators that are biased exactly at midpoint is because I want active lows only at 1.65 and not above or below it.
2. But regenerative comparators i.e positive feedback comparators don't give that kind of an action as they pull the o/p to rails once they recognize an i/p below the bias point of 1.65volts.
3. So if I am designing a transistor level analog CMOS circuit , then are you telling me that I cannot design a window comparator to work at a speed of 30ns?

Thanks for all your help!!!

Sumera

I have numbered your points.
1. I don't understand this since you can bias a comparitor anywhere between Vcc and gnd (or lower if you have negative rail)

2. I don't understand this since either. All the hystersis does is to shift the trigger point by a few millivolts in order to provide a fast response, ie. to speed up the transistion by positive feedback.

3. I did not mean to imply this. I don't know anything about IC design. I only design circuits using ICs designed by someone else.

Len

 

[spatan]

thank you

Thanks a lot Len for all your help and time!!!!! I should have told you in the beginning that I want to design an IC circuit. I think there is another way I can do my circuit w/o using teh window comparator. I still have a lot to figuring out to do.

Thanks,
Sumera

 

[ljcox]

Re: thank you

Thanks a lot Len for all your help and time!!!!! I should have told you in the beginning that I want to design an IC circuit. I think there is another way I can do my circuit w/o using teh window comparator. I still have a lot to figuring out to do.

Thanks,
Sumera

You're welcome.

It does not really matter that you are designing an IC. The principles that I and others have mentioned are still applicable.

Len