HELP ME IN VERILOG CODING

[NITHEESH]

here i am adding the code for 3 modules counter,pid and pwm...plzz help me to link these three modules....in such a way that i want the output of counter to be given as the error signal input of pid(e_in) and the out put of pid (u_out) as the the input of pwm(switches)....plzz help....thanks in advance..

Code:
module count(clk,a,out,r,n,e);
input clk;
input a;
input [7:0]r;
input [7:0]n;
integer counter=0;
output reg [7:0]e;
output reg [7:0]out;
reg [7:0]temp;
always @ (a)
begin
if (a==1) counter=counter+1;
temp=(counter/r);
out=(temp*n);
if
(out>=200) e=out-200;
else
e=200-out;
end
endmodule




Code:
module PIDdddd(u_out,e_in,clk,reset,u);
output signed [15:0] u_out;
output signed [15:0] u;
input signed [15:0] e_in;
input clk;
input reset;
parameter k1=107;
parameter k2 = 104;
parameter k3 = 2;
reg signed [15:0] u_prev;
reg signed [15:0] e_prev1;
reg signed [15:0] e_prev2;
assign err=(e_in/5);
assign u =(u_prev)+(k1*err)+(k3*e_prev2);
assign u_out = u+(-(k2*e_prev1));
always @ (posedge clk)
if (reset == 1) begin
u_prev <= 0;
e_prev1 <= 0;
e_prev2 <= 0;
end
else begin
e_prev2 <= e_prev1;
e_prev1 <= err;
u_prev <= u_out;
end
endmodule


Code:
module pulse(clk,switches,pwm);
input clk;
input [16:0] switches;
output pwm;
reg pwm;
reg [15:0] counter=0;
parameter sd=195;
always @ (posedge clk)
begin
counter=counter+5;
if(counter<=switches*sd) pwm=1;
else pwm=0;
if (counter>=50000) counter=0;
end
endmodule