AD_CS BIT P1.0 ;CS, CK and DO fitted to port 1
AD_CK BIT P1.1
AD_DO BIT P1.2
AD_RESULT equ 030h; ;This variable holds result from A/D conversion.
;
MOV P1, 0FFh
CLR AD_CK
CLR AD_CS ;Select chip (initiate conversion)
;
MOV R1, #02h
;
PREPARE: SETB AD_CK ;MUX settling time
ACALL delay_us
CLR AD_CK
ACALL delay_us
DJNZ R1, PREPARE
MOV R2,AD_RESULT
MOV R1, #08h ;Read in value from A/D convertor, 8 BITS
CONVERSION: SETB AD_CK
ACALL delay_us
MOV C, AD_DO
MOV A, R2
RLC A ;Left because MSB comes in first
MOV R2, A
CLR AD_CK
ACALL delay_us
DJNZ R1, CONVERSION
MOV AD_RESULT, R2
SETB AD_CK ;cycle clock once.
ACALL delay_us;
CLR AD_CK
ACALL delay_us;
SETB AD_CS ;Deselect chip.
delay_us: ;FOR STANDARD 12 CYCLE and 11.0592 MHz
MOV R3, #05h ;10 uS
DJNZ R3, $
RET