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Grounding a Kiloamp kickback pulse

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Mosaic

Well-Known Member
Hello:
I have to handle a kiloamp kick back pulse, perhaps 50ns rise time, 1000ns fall time.
Will dumping it to ground be risky if the ground is shared with an MCu?

I am worried about ground bounce.

Should i include an inductance/ferrite bead in the ground between the kick back and the MCu ground for isolation? Or just use a star connection off the main ground, to isolate ground currents?
 
Last edited:
1000A pulse, 50nS:
You should return the energy to where it comes from.
Please send a schematic of the area with the 1kA current. What voltage? What switch?
 
I am worried about ground bounce.
I would be, too! The star connection would be a start. Presumably the MCU's positive supply rail would be thoroughly decoupled and referenced to a point not subject to the high current.
 
I am switching a similar Kilo A pulse ( <160 uSec @ 120Hz, into a lead acid batt for desulfation) via an NFET bank on the ground rail, perhaps 35VDC peak into the 12V batt from low ESR caps. Spice says i will see a >1KA kickback for 1 uSec (rise & fall) at around 60V (NFet avalanche breakdown). IRLB3036pbf NFETS are used.

The 12V battery model is a 22nF series inductance with a 1.5 F parallel capacitance. Pulse circuit resistance is <15 milli ohms incl NFEts (.001), CAP ESR (.004) and wire losses (.004) and battery int resistance (.005).

The supply is from a rewound MOT delivering about 35VDC @ 10A.

However, the micro controller supply is from another winding, but I planned to ground reference the two supplies after each full wave bridge. I was wondering how best to to handle that spike returning to the pulse winding. Also I am wondering what it might do to the full wave bridge.

Have a look at the sim.
 

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Are you sure you should have the inductance in your model?
 
Well all batteries have a bit of inductcance.
But I've been doing some maths:


If I remove the avalanche bypass circuit on the lower right. With 6 NFETs in the pulse bank I note just 30Amps per NFET avalanche. 180 AMPS total.
It appears that this +ve 1uSec current ends up at the 30K uF cap bank -ve rail, thus discharging it a bit. Some probably passes thru to the B+ rail, but cannot go pass the inductor in the Pi filter and gets snubbed.
If I use irfp3306 NFETS @ 100 C junction temp operating conditions they can handle 60mJ avalanche energy at that duty cycle.
https://www.electro-tech-online.com/custompdfs/2013/03/44063.pdf

Actual pulse energy is VIT = 60 x 30 x .000001 = 1.8mJ.

I guess that works.
 
I think your real world circuit is not going to work like your spice circuit.
How are you going to turn off 6 FETs that fast. The gate current is very large to turn off one large FET in 50nS.
You need very short wires or there will be more inductance than you want.
If you turn off the FETs slowly there will be no spike.
You can put a RC snubber (or RCD) across the FETs.

I would put a gate driver IC at each FET. A snubber on each FET. And tie the ground of the micro to the source of the FETs. (star ground with center at the source(s).)
 
Thx, will do. I have a couple of MCP 1407 chips ganged to do that.
I will drop the number of Fets to 4 given their avalanche abilities.
I'll run a thermistor on them to see if they're heating up, if so I may have to snub.

Just talking abt this helped me see it more clearly.

BTW should I tie the full wave bridge grounds to the 120V 3-pin supply ground as a better means to handle ground currents?
 
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