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Global variables in VHDL

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Hi!
Hey, im new to VHDL. I need some help from you, if u can. I have written some entities separately and the entities use certain variables. I now need to create a top level entity which included all these lower level entities. The thing is, some of the variables needs to be accessed by all these entities, ie, something like a global variables we use in C.
Like for example, if im creating a calculator, iv defined the addition, subtraction, mul as different entities, now they must all be access and write their value to a single variable called result.
How can i do this using VHDL? Can u please give me some suggestions? Thanks!!!

Bala
 
Do you know how this "global" register is implemented - is it a tristate bus, a big multiplexer, a massive multiport ram? Because the VHDL compiler doesn't know either. You need to specifiy how these ports if the different entities are connected *explicitly*.
 
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