Gate delays

[ljcox]

Does anyone know whether the low to high and high to low delays through a gate are similar? Or are they unrelated?

For example, the 74AC02 NOR data sheet states L>H 1.5, 4.0, 6.0 ns (min, typ, max) and H>L 1.5, 4.5, 6.0 ns.

So if I measured the H>L delay of a particular 74AC02, and it was say 3.1 ns, would the L>H delay also be around 3.1 or could it be significantly different, say 4.3 ns?

Len

 

[Optikon]

Does anyone know whether the low to high and high to low delays through a gate are similar? Or are they unrelated?

For example, the 74AC02 NOR data sheet states L>H 1.5, 4.0, 6.0 ns (min, typ, max) and H>L 1.5, 4.5, 6.0 ns.

So if I measured the H>L delay of a particular 74AC02, and it was say 3.1 ns, would the L>H delay also be around 3.1 or could it be significantly different, say 4.3 ns?

Len

Yes they tend to be similar on for certain types of logic.

No, they really are not related.

Both specs depend on the output stage in the circuit. In the CMOS part, you have FETS saturating to the rail depending on output. They do this very quickly and so the H>L & L>H times are of the same order.

But, if you use an open collector/drain part with external pull up resistor, then your L>H time is controlled by that resistor and is thus completely unrelated and dissimilar to the H>L time of that part.

So it depends... and if it is active drive H&L then usually similar.. but not necessarily related.

 

[ljcox]

Thanks for the response. I think we may be interpreting the word "related" differently.

I meant it to mean "of the same order" and your reply seems to indicate that the H>L and L>H times for a given gate are "related" in my sense.

For example, if a gate has a L>H delay of say 1.9 ns, then the H>L delay will be similar, eg. 2.2 ns. It is not likely to be say 4.6 ns.

Is this what you meant?

Len

 

[Optikon]

Thanks for the response. I think we may be interpreting the word "related" differently.

I meant it to mean "of the same order" and your reply seems to indicate that the H>L and L>H times for a given gate are "related" in my sense.

For example, if a gate has a L>H delay of say 1.9 ns, then the H>L delay will be similar, eg. 2.2 ns. It is not likely to be say 4.6 ns.

Is this what you meant?

Len

Using your sense of the term "related", they will be related if the logic output stage is NON-open collector/drain as the switching technology there will be of the same Order in switching speeds on & off.

If you pick out logic parts that ARE open collector/drain, they will not be "related" as you will find that the part can turn on (sink current) much faster than it can turn off (due to output capacitance acting with your pull up resistor) shrinking the size of the pull up will speed it up at the expense of burning more power and you can only take this to the limit of what the part can sink.

I can find an open drain logic part that can sink current and be at a valid logic low in < 10ns. Now if I put a 50k pull up resistor on that part it will switch back high in as long as 1us which is 100 times slower than it can turn on so the H>L and L>H times are NOT at all "related" they differ by two orders of magnitude.

 

[ljcox]

Thanks again. Sorry, I forgot to say that the IC is not an open collector/drain type. I understand that point.

Len