Full duplex communication using SPI

[p.gholap93]

This is first time I am using SPI to achieve full duplex communication between two Atmega 128.
Master has held controlled SS pin low while transmitting data and the pin is SET once data has been transmitted.
My Slave is receiving data transmitted by Master but Master is not receiving the data transmitted by Slave.
I also attach C code files of Master as well as Slave.
USART is initialized just to confirm whether data has been received or not.
I also attach simulation file(PROTEUS).
So please help me to overcome this problem.

 

[wkrug]

I've not much experienxe with SPI too, but it is possible to late write Data into the SPDR when SS Port is low and transmission is in progress.

I would to try to make the transmission in 2 Steps.
In first step write the byte from master to slave.
In Master Routine wait a little bit to give slave a chance to write back his data to SPDR.
Then master can read the bytes from slave.

Another possible way can be to wait a little bit after set the port of !SS in master.
That give slave a chance to write into SPDR.

Another Question:
Do you use the MISO, MOSI, CLK, !SS Pins for transmission ?
Or an USART ?

 

[p.gholap93]

no i used MISO MOSI AND !SS foe transmission
USART is used just to print received data
by the way i'm clear about your solution
how to achieve it through programming?

 

[wkrug]

I think you compiler knows the command delay_ms(xx) or delay_us(xx).
In my compiler it is containend in the delay.h library.
So you can get defined delays in your program.

 

[p.gholap93]

I have given delay of 5ms in Master programme to wait for slave to load data into SPDR. But still Master is not receiving data.
One more interesting thing is that,in my slave programme i have given the condition so that Slave will first check whether its !ss pin is held low or not and if it is low then only Slave will transmit/receive data as is required.
But if I remove the condition and call the function to transfer/receive data in Slave programme then Master receives data.
So can any guess now what could be the problem?

 

[wkrug]

I've found that in the Datasheet of ATMEGA64 Controller at Page 165:

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of transmission
flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested. The Slave may continue to place new data to be sent into SPDR before reading the
incoming data. The last incoming byte will be kept in the buffer register for later use.

When i understand right, the Data must be in SPDR before the !SS line is low.
The sending Data must be written in the SPDR register before the incoming data is readed.

 

[p.gholap93]

well thank you very much. Your idea really worked.