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# Frequency Doubler with Logic

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#### ethan169

##### New Member
Ok guys,

Im trying to figure out how to create a frequency doubler to be used on a FPGA. Im using the quick logic FPGA that's kind of a one shot burn in FPGA. So unfortunately it doesn't have a frequency double block like the xzylinx does. Forgive me if butchered the spelling of their name.

So i know if I can somehow take an original signal delay it slightly or maybe by %50 and then XOR the two signals together I have essentially what im looking for. But my problem is how do I delay one signal short from chaining a bunch of gates together to use the delay they have internally (thats kind of mickey mouse and im not even sure if it will work)

So any ideas on where to start with either delaying or creating a doubler with just logic? Im trying to do this without using external capacitors etc. So 555's are out as well as other external circuits.

Thanks in advance for any ideas!

-Ethan

Hello,

Oh, no caps? That's too bad, cause i know a way using two small caps and
a logical AND (negative logic OR) gate and an inverter. Output isnt always a
50 percent duty cycle however.

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Frequency multiplication isn't really an option in FPGA's that don't have Pll's. Better to double the frequency off-chip, then use flip-flops to divide it internally to get the ratios you want.

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Hmmm.

Not the answers i was looking to hear. I guess Ill have to do something externally. More PCB stuff I have to incorporate which I'm trying to keep to a minimum.

Thanks for the info guys!

-Ethan

You can use a 2-input exclusive-or gate with an even number of many inverter gates in series connected to one of the inputs. Drive the inverter gates and the other exclusive-or input with the clock you want to double. You will get a short pulse at the exclusive-or output at each clock transition with the pulse width equal to the combined gate delays of all the inverters.

Do it in software? Just detect each edge / and \ of the incoming waveform and soft generate a short "event" /\ for each incoming edge.

Like Cruts said, an XOR with logic delays in line ( Or string of logic blocks in FPGA, a delay line would make a more 50% duty cycle) is the way to go. See this app note.

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If you have spare pins on the FPGA, you can simply install a clock on the board that is 2X the frequency, then use the FPGA to divide the clock for the board. No additional logic needed.

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