Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

frequency division in verilog

Status
Not open for further replies.

mjunaid61

New Member
Hi,
I have a frequency of 25MHz and I want to decrease it to 11MHz using FPGA
. the ratio between the frequencies is 2.25 which will generate 11.11
MHz.
The question is how to divide 25MHz by a factor of 2.25

Any help will be appreciated
Thanks
 
You have to multiply by 4/9. It can only be done by using a PLL to multiply the base frequency by 4, then you use a divider chain to divide by 9.
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top