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But every time will it be 8 bit or 10 bit? Because as per the data sheet information the resolution is changing, even though the pdc register is 16 bit for duty cycle. It keeps varying based on the pwm frequency I think. Can you please help me understand. I am not sure if i am following or i am deviating from the actual question. Does fractional duty cycle in percentages and the resolution have any relation?
If you look at the PDCx value, you will notice that the number of bits set is the same as the resolution. I.E. 0x3fff = 11 1111 1111 = 10 bits set. This is the value that the counter resets at and so the max PWM value is the same as this max value. However, because the counter is being clocked at a certain frequency then the frequency drops as the value of PDC increases. E.G. at 10MHz and PDC value of 0x1ff (512 steps) the frequency is 10,000,000/512 = 19.5kHz - at 20MHz = 39.1 etc.
One final question take the example of 1st one. Max my PDC is 0xFFFF. So if i load 65535 i will get 100% duty. Now let us say i load 65534 into PDC register then what will be my duty? Will it be (65534/65535)*100%? And 1 bit corresponds to (1/65535)*100%. Please advise.
My bad 2^16 is 65536 not 65535.
but i stand by my logic that you need to do 1/(65536-1), so 1 divide by one less than the number of states
Perhaps i'm being dumb, but I've talked through it below.
if i simplify it to just 2 bits for example.
2^2 gives me four states:
00 is state 1 (not state 0) and would be 0% duty cycle
11 is state 4 and would give 100% duty cycle.
if i just divide 1 by the number of states (1/4) as Pommie has done then i get each bit equal to 25%
But that's not right. In state 1 (00) i have 0% duty but the above suggests i should have 25%
instead if i say 1 divided by the number of state less 1 [ 1 / (4-1) OR (1/3) ]. that gives me 33% per bit
so state 1 is (1-1 * 33) = 0% duty which is correct
2 is (2-1 * 33) = 33.3%
3 (3-1 * 33) = 66.6%
4 (4-1*33) = 99.9%