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fpga accumulator

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spark

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does anyone know a good way of implementing a 10-bit accumulator uding VHDL? i tryed doing a process as follows - clock in the data, perform the addition, and store the answer in a register, to be added to new input on the next clock. i'm having problems with my simulation - the contents of this register going unknown on the first addition. thanks.
 
Make sure you have a reset input that sets the register to a known value. 'U' + something = 'U'. In your simulation toggle the reset line before you do anything.
 
Why not...

Starting with zero, perhaps?

Initializing digital circuits should be second nature I think. Why not here. Zero is, simple, easy and always the same.
 
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