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Flip Flops

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ae4jm

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I have a digital electronics class in college where I'm enrolled for industrial electronics. I've really had no problems picking up the combinational logic circuits, but these sequential logic circuits, some are difficult to understand.

How in your opinion would it be easier for me to understand the RS flip flop, JK flip flop, and D flip flops (clocked and not clocked)? Do you guys have a easy way of remembering them? We have a mid term coming up where we must build an experimental tachometer using a 4553, 555, 74HC04, 4543, 4 seven segment displays, 3 transistors, and a few caps and resistors, gonna feed a clock pulse and an trigger pulse into the circuit. I have the schematic that we have to build this circuit from so there shouldn't be a problem building this circuit, I'd just like to have a better understanding of how these flip flops work so that I can get a better understanding.

Thanks,
Matt
 
All flip flops are basically the same....

The RS Flip Flop is the most basic. The D flip flop is a modification of RS. The JK uses the output to control the inputs. Simillary the Master Slave FF.

The RS FF is the core of them all.
 
In the RS flip-flop, SET makes the Q=1 (high), RESET makes Q=0 (low). In the D flip-flop, whatever is on the D input when clocked is transferred to the Q output. There is no such thing as a non-clocked D flip-flop. I have avoided the JK flip-flop because I never took the time to understand it!
 
Flip-Flops

Thanks Gentlemen,

I really appreciate these two explanations. I will study these concepts along with my text book to get a better understanding. You know, most things out of our books I can comprehend by just reading. But these flip flops, it really helps building a circuit and seeing it work, also the other guys in the class, seeing their circuits work. But probably the best thing that helps me is seeing these circuits in which they don't work and then helping to troubleshoot them gives me the best understanding.

Again, thanks very much for the quick response and I really appreciate the help and understanding in flip-flops.

Thanks,
Matt
 
the jk

the explanations of the rs and d type are spot on, the jk is different tho....

If you connect the j and k inputs to a permenant logic 1 this puts the jk in 'toggle mode'. when the clk input has a clock on it in toggle mode, the outputs Q and not Q will toggle between logic High and logic low at half the rate at which the jk is clocked (twice as slow).

If you connect the Q output of one jk into the clk input of the next jk, then that doubles the time again (4 times as slow as th originall)

hope this makes you better understand the chip mate
 
Have you done a search in this forum for Flip Flops? They have been discussed many times.

The JK is very useful since it is controlled by the state of the J & K inputs.

Truth table:-

J K Q
0 0 no change
0 1 If high, goes low at clk pulse and remains low after subsequent pulses.
1 0 If low, goes high at clk pulse and remains high after subsequent pulses.
1 1 Toggles, ie. changes state at each clk pulse
 
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