Flip-Flop Characteristic on Power-Up

[Loki]

The output of , for example, a D-FF is unknown on power-up. Am I correct? If I'm correct, then could you please tell me how to get rid of this unknown signal and pull it down or up.


Regards

 

[williB]

Re: Flip-Flop Characteristic on Power-On

The output of , for example, a D-FF is unknown on power-on. Am I correct? If I'm correct, then could you please tell me how to get rid of this unknown signal and pull it down or up.


Regards

..the output of a D type FF is whatever is at the input during power up..
simply apply a logic low to the D input on power up will give you a low on P/U..
NOTE If this chip (which one ?) has a preset and clear the above explanation is moot..

 

[Loki]

>> the output of a D type FF is whatever is at the input during power up
simply apply a logic low to the D input on power up will give you a low on P/U <<

This is my problem. I have to apply logic 1 all the time, but I need logic 0 on power-up at the output pin. I think I need some kind of logic here. The chip is 74HC74, which has asynchronous set and reset ability.

 

[williB]

i need more info ..

 

[williB]

is this a theoretical or practical question

 

[Loki]

is this a theoretical or practical question

Both theoretical and practical. What kind of difference does it make?

 

[williB]

well if you had an actual circuit ..i could ask how come you cant apply a logic zero...

 

[e]

you can do it with an RC charging circuit on the preset pin, this will set the logic when power is applied, check the net for more info

 

[Loki]

well if you had an actual circuit ..i could ask how come you cant apply a logic zero...

I have a timing diagram of 3 signals (Q,CLK,S1). Using 2 of them(CLK,S1), I am trying to create the third signal. (Q) For this purpose I use a D-FF whose clock signal is provided by the CLK signal, whose asynch. reset signal is provided by S1 and lastly whose input signal is logic 1. However as you can see from the graph, which is obtained by OrCAD simulation of this simple circuit, output signal (Q) is undetermined in the beginning. I didn't want to set FF initial outputs as zero or one by the software.

Now, what do you think?

 

[Roff]

I don't understand how you got that result. 74HC74 has active low set and reset. Since S1 (reset) is low at clock time, the Q output should stay low at all times.

 

[Loki]

I don't understand how you got that result. 74HC74 has active low set and reset. Since S1 (reset) is low at clock time, the Q output should stay low at all times.

i just invert the S1 signal.

 

[Roff]

I don't understand how you got that result. 74HC74 has active low set and reset. Since S1 (reset) is low at clock time, the Q output should stay low at all times.

i just invert the S1 signal.

You should have said that.
To force the Q output low on power up, use the circuit below. The R1*C1 time constant depends on your power supply turn-on rise time, but 10ms - 100ms should be OK.