Estimation of Transistor Parameters?

[DigiTan]

As part of my battery switchover project, I need to bias a P-Channel MOSFET to go into conduction as one of the power sources drops out. (I'll edit in the schematic when I get back home).

I know that the current in saturation mode is a function of gate-source voltage (Vgs), threshold (Vt), the process transconductance parameter (kp'), and the channel aspect ratio (W/L). So far so good. The problem is: neither kp' nor W/L are specified in the data sheet. [data] I planned on using the datasheet's discreet plots on page 3 to calculate kp' and W/L. The story should go:

kp' (W/L) = 2*Id / (Vgs -Vt)²

...But this is yeilding suspiciously large figures (790mA/V² as opposed to the 1mA/V² range I was expecting). Before I go in monday to verify this manually, I want to check with the forum. The discrete plots are nice, but I really need an equation like this since I want the optimal bias.

Is 790mA/V² a reasonable value for kp'(W/L)?

 

[Roff]

I never heard of anyone using that equation unless they were designing MOSFETs, or ICs containing MOSFETs. That's why you don't find them in datasheets. What are you trying to do now?

 

[Oznog]

You would not use this equation. The spec sheet show Id vs Vgs. It sounds like want this in a switching mode. You should note the chart they show for Rds-on vs Vgs as this has a strong effect on its behavior as an on-off switch.

 

[DigiTan]

This one's sort of a follow-up to my Depletion MOSFET for supply switch? question from last month. Originally, I was planning to use the FET as a switch. During testing, I found out that if 6V-8V adapters were used, the FET would not be conduction, and that was letting the output to fall from 5.7 Volts to 3.2 (do'h). I want to advertise the system as being able to use virtually any adapter voltage, so I'll have to get rid of that coverage gap. Unfortuanantly, at my college they only care about equations and theory, which is partly why I'm transferring out this summer.

Anyway, I want to bias the gate so that the FET will turn on (Vt = 3.5V from the datasheet) when the voltage out of the 78L06 reg falls to 5.5 Volts are less. Since the current at that point is still very small, I was hoping to get an equation to let me know how bad the voltage will dip for low-voltage adapaters.

 

[Roff]

Why would you use a 6 volt adapter in front of a 6 volt regulator? Are you planning on using an LDO regulator?
I ran a sim using Fairchild's FDN304PZ, which is spec'ed down to -1.8V Vgs (100 milliohms at that voltage). The voltage dipped from 5.7V to 4.8V before the battery cut in.
They have one PMOS spec'ed down to 1.5V (can't remember the part number), but they don't have a Spice model for it.

 

[DigiTan]

Why would you use a 6 volt adapter in front of a 6 volt regulator? Are you planning on using an LDO regulator?

I'm publishing the design for a large group of graphing calculator programmers. Since it's a diverse community, I want the switchover to work with whatever DC adapters these people have available. I plan to lable 9V - 27V as the preferred adapter voltages, and 8V - 4V as being able to 'assist' the batteries.

I guess the FDN304PZ stayed above 4.7V because of a lower threshold. I was also use a 240Ω load. After testing my calculator yesterday, I found out voltages bewteen 4.50 and 6.61 Volts will be acceptable, so that gives me a little more error room.

My concern now is that steep dropout at the 4.7V point. If the user's adapter is poorly regulated, that steep curve might exagarrate the ripple and reset the machine. I haven't tested the calculator's ripple tolerance yet, so I can't speculate on whether that'll be a problem. A guessing the regulator's ripple rejection is very low for adapters below the 6 Volt point. :?