Embedded system with 250+ IO?

[VanDerSnow]

Hello all,

Looking for people opinions on how to implement embedded solution with 250+ IO's.

The system would work in such principle that one pin is set to output while all others are inputs. Then it changes to next pin being output and all others inputs.

Looked at IO expanders and potentially using multiple MCU's, but what are your thoughts?

 

[rjenkinsgb]

You can very simply expand inputs and outputs using shift registers - parallel load ones for inputs and parallel latched out ones for outputs. Cascade all input ones and separately all output ones, then use an SPI port to simultaneously transfer the appropriate number of bytes out/in, pulsing the input latch signal beforehand and the output last signal after the transfer.

Five pins, unlimited I/O

The 74HC165 or HC166 should work for inputs

https://www.ti.com/lit/ds/sdas156d/sdas156d.pdf?ts=1626260274428&ref_url=https%253A%252F%252Fwww.google.co.uk%252F

The 74HC595 is often used for outputs:
**broken link removed**

 

[danadak]

Maybe modify Verilog code to manage pin turn around -

64 Bit Serial In Parallel Out Shift Register

Hi, I have seen users occasionally needing large I/O expanders, cascading some off the shelf parts to get enough I/O. This was done in Verilog, features set/clr/load. Note design shown Serout and Serin were tied together to do some testing...

www.electro-tech-online.com

But would seem to me this is a natural for FPGA to squeeze into a single package.

Another approach is RAM based rather than straight sequential logic.


Regards, Dana.

 

[VanDerSnow]

You can very simply expand inputs and outputs using shift registers - parallel load ones for inputs and parallel latched out ones for outputs. Cascade all input ones and separately all output ones, then use an SPI port to simultaneously transfer the appropriate number of bytes out/in, pulsing the input latch signal beforehand and the output last signal after the transfer.

Five pins, unlimited I/O

The 74HC165 or HC166 should work for inputs

https://www.ti.com/lit/ds/sdas156d/sdas156d.pdf?ts=1626260274428&ref_url=https%253A%252F%252Fwww.google.co.uk%252F

The 74HC595 is often used for outputs:
**broken link removed**

Thanks for you suggestion.

Apologies my ignorance but does this means one pin from output register would be joined with one pin from input register?

As every single pin (lets say 250 pins in total) must be input and output.

 

[Nigel Goodwin]

Thanks for you suggestion.

Apologies my ignorance but does this means one pin from output register would be joined with one pin from input register?

As every single pin (lets say 250 pins in total) must be input and output.

What EXACTLY are you trying to do (not just how you think to do it), which makes a big difference to suggestions.

 

[ronsimpson]

MCP23016; there is a thing called i/o expander. In this case it is I2C but there are SPI versions and parallel versions. This one is 16 bit but there is a8 bit version. This part you can set each pin as I or O. By using A0,1,2 you can have 8 devices on the same bus.

 

[Pommie]

What EXACTLY are you trying to do (not just how you think to do it), which makes a big difference to suggestions.

Agree completely, there are many ways to do this but without knowing what you're trying to do makes it difficult to suggest one.

Mike.
Edit, for example, to drive 400 LEDs does not require 400 I/O, it can be done with 40 driving a 20x20 matrix.

 

[rjenkinsgb]

Apologies my ignorance but does this means one pin from output register would be joined with one pin from input register?

No; each 74HC166 provides eight inputs and each 74HC595 provides eight outputs, all completely independent of each other.

It's up to you what you put in the SPI transmit buffer for each output byte, eg. copy from RAM that you use as "outputs" within the program.

Likewise, with each SPI byte transfer, you store the received bytes in a locations and use them as the "inputs" in your program.

You have a separate routine that does the SPI I/O transfers on a regular schedule, or at the end of each program loop, to the RAM copes are constantly synchronised with the real I/O signals.

That's pretty much how industrial PLCs work, often using some form of serial data chained through all the I/O expansion and copying to/from RAM areas before or after each program pass in the main loop.

This is an example using two SRs each for inputs and outputs; you can use as many as you like, within reason.
It also uses the same pin to latch both the outputs and inputs between the SPI transfers, so only four pins used.

Ignore the pin numbers, they will vary with the device being used - using an SPI port, they would be, top to bottom:
SPI Data out, SPI Clock, a general output pin for the latch pulse, and SPI Data in.

As others say, there are various dedicated I/O expanders which may be more convenient in some situations - but SPI on a device that has a hardware SPI port is the fastest and has lowest overhead, as it can run at megabit speeds and needs no handshaking or waiting for remote devices.


Edit - reading the original post again, do you actually want the same pin as alternately output and input?
As long as the output is a fixed polarity drive (eg. "open collector " style) , that system could work by linking the outputs to inputs with diodes and connecting the external signal and a pull-up resistor to the input pin.

 

[VanDerSnow]

No; each 74HC166 provides eight inputs and each 74HC595 provides eight outputs, all completely independent of each other.

It's up to you what you put in the SPI transmit buffer for each output byte, eg. copy from RAM that you use as "outputs" within the program.

Likewise, with each SPI byte transfer, you store the received bytes in a locations and use them as the "inputs" in your program.

You have a separate routine that does the SPI I/O transfers on a regular schedule, or at the end of each program loop, to the RAM copes are constantly synchronised with the real I/O signals.

That's pretty much how industrial PLCs work, often using some form of serial data chained through all the I/O expansion and copying to/from RAM areas before or after each program pass in the main loop.

This is an example using two SRs each for inputs and outputs; you can use as many as you like, within reason.
It also uses the same pin to latch both the outputs and inputs between the SPI transfers, so only four pins used.

Ignore the pin numbers, they will vary with the device being used - using an SPI port, they would be, top to bottom:
SPI Data out, SPI Clock, a general output pin for the latch pulse, and SPI Data in.

As others say, there are various dedicated I/O expanders which may be more convenient in some situations - but SPI on a device that has a hardware SPI port is the fastest and has lowest overhead, as it can run at megabit speeds and needs no handshaking or waiting for remote devices.


Edit - reading the original post again, do you actually want the same pin as alternately output and input?
As long as the output is a fixed polarity drive (eg. "open collector " style) , that system could work by linking the outputs to inputs with diodes and connecting the external signal and a pull-up resistor to the input pin.

Yes, as in terms of your statement in the end.

The device would check continuity in the cables which may have diodes or resistors fitted.

So from operational point of view - you send either High or Low (this can be driven by design) from one particular pin while all remaining pins receiving it, then next cycle is to run H or L from another pin while others receiving. So every single pin is Input and Output. Hope this makes it clearer

 

[VanDerSnow]

MCP23016; there is a thing called i/o expander. In this case it is I2C but there are SPI versions and parallel versions. This one is 16 bit but there is a8 bit version. This part you can set each pin as I or O. By using A0,1,2 you can have 8 devices on the same bus.
View attachment 132456

From memory when I looked at IO expanders it had some limitations too. My research was while ago so maybe today there's more choice of such expanders.

 

[Pommie]

The device would check continuity in the cables which may have diodes or resistors fitted.

If the cables have diodes fitted than a matrix can check all cables with the square root of the number (of cables) doubled, I/O pins.

Mike.

 

[VanDerSnow]

If the cables have diodes fitted than a matrix can check all cables with the square root of the number (of cables) doubled, I/O pins.

Mike.

Mike,

The cables may have diodes fitted, or may have just few or none, not yet known hence it would be good to cover worst case scenario.

 

[Pommie]

If the cables have diodes the wrong way then they'll read open circuit or do you need to check both ways? Charlieplexing may be able to work both ways. Most Micros can have pins in three states so checking a 20x20 matrix for conduction both ways is fairly trivial. However, still guessing what you're trying to do!!

Mike.

 

[VanDerSnow]

If the cables have diodes the wrong way then they'll read open circuit or do you need to check both ways? Charlieplexing may be able to work both ways. Most Micros can have pins in three states so checking a 20x20 matrix for conduction both ways is fairly trivial. However, still guessing what you're trying to do!!

Mike.

I thought it's already obvious this device would check connections in cable harness or PCB. Both can have resistors and diodes. Worth to mention PCB's would be mainly distribution style, so no complex circuitry (no IC's etc.)

You are on right path - if you set one pin high per each check cycle, at one point the device would be able to identify whether diode is fitted in correct orientation.

However such feature may add too much complexity as I'm not that deep in to embedded systems, however always up to learn something new.

 

[rjenkinsgb]

OK, I think I have a way to do it; it needs twice the number of output bits (via shift registers) as test connections.

Alternate outputs would have a diode to the test point (for low signal) and a PNP transistor or P channel FET to the same test point to give the high level signal; plus an input from the test point using another set of shift registers.

And, most critically, a resistor from every test point to a common point that can be driven high or low by a separate MCU output.

The output shift registers could be controlled by normal MCU outputs, as it would just have a single low bit clocked in then the data high for the duration of the test cycle.

Each time the output register was clocked, it would shift the single bit along one place, forcing a test point low, then high, then the next one low etc.

The feed to the resistors would need setting to the inverse polarity at each stage, to set the level on the inputs that were not driver from that test output.

The whole input shift register setup would need reading after every output bit stage, to get the levels produced..

 

[danadak]

Most modern processors can config a pin to be bidirectional. Using internal
pullup pin can drive out, and its input register read the pin by driving a 1 onto
pin and reading if its being pulled down by external driver.

Note in some parts pin can function both as analog and digital. Leads to some
interesting design possibilities.

https://www.cypress.com/file/45381/download

Regards, Dana.

 

[VanDerSnow]

OK, I think I have a way to do it; it needs twice the number of output bits (via shift registers) as test connections.

Alternate outputs would have a diode to the test point (for low signal) and a PNP transistor or P channel FET to the same test point to give the high level signal; plus an input from the test point using another set of shift registers.

And, most critically, a resistor from every test point to a common point that can be driven high or low by a separate MCU output.

The output shift registers could be controlled by normal MCU outputs, as it would just have a single low bit clocked in then the data high for the duration of the test cycle.

Each time the output register was clocked, it would shift the single bit along one place, forcing a test point low, then high, then the next one low etc.

The feed to the resistors would need setting to the inverse polarity at each stage, to set the level on the inputs that were not driver from that test output.

The whole input shift register setup would need reading after every output bit stage, to get the levels produced..

This sounds like analog-style circuitry vs what Dana has suggested (more of a modern IC solution).

I'm interested in both - one is a bit difficult to read from text, a schematic would probably be easier to understand the logic.

Modern MCU is unlikely to have ~250 GPIO's, therefore would you (Dana) suggest multiple MCU's in this case?

Edit: quick search returns STM32F730I8 as potential option as it has 138 GPIO's, so two of them would be enough.

 

[Pommie]

OK, I now think (but still not sure) that you want to test a cable loom for continuity. Is that shorts between conductors, connections from one end to the other, something else?

Mike.

 

[ronsimpson]

IO expanders it had some limitations

Like what? The one I pointed to has a bit for each pin to make I or O and also a bit to invert the logic. Some expanders have pins that are both I & O at the same time and that can be hard to understand.

 

[Pommie]

Some expanders have pins that are both I & O at the same time and that can be hard to understand.

You need to explain that. Or is it simply OC?

Mike.