As Nigel said the question is pretty vague. That data transfer rate requires you to write a byte every 2.44 microseconds. I don't think there is any EEPROM technology that can work at that speed. Using battery backed up RAM is the only other option I can imagine.
The concept is straight forward, but the devil is in the details. Take a garden variety SRAM chip of size 64K x 8. Connect the Vcc pin through a Schottky diode to a suitable battery. Also connect the system power supply to the Vcc pin of the RAM chip, again through a Schottky diode. The RAM chip will derive it's Vcc power either from the system power supply or from the battery. When the RAM chip is running from the battery it is important that the control signal like Chip Select(CS*), Output Eneable(OE*), and Write Enable(WR*) be held in inactive stable states. In this condition the RAM chip will retain its data down to 2.0V or possibly less.
I'm not familiar with an MMC. I could Google it, but this is your thread.
Common EEPROM do not support 20 microsecond write cycles bulked or not bulk writing.
Approach it this way. 6Kbits for 8-bit parallel = 750 bytes in 15 ms. Converted to seconds is 50Kbytes per second writing rate. Now invert to get the 1/50,000 = 20 micosecond write cycle times per byte. So you need nonvolatile ram to write/read an 8-bit parallel byte under 20 microseconds.
If 8-bit parallel is fixed then rule out all serial rams. Rule out all rams with read/write cycles > 20 microseconds. Try to use rams faster than 20 microsends to compensate for address and page times and fudgers alike. You have to consider the addressing method. Serial addressing busses will limit your transfer speed if auto address incrementation is not supported in the ram chip. Parallel addressing bussed rams will require alot of i/o real estate Those Dallas chips reference by ericgibbs are one solution.