A PIC has a two level UART receive buffer. The UART can hold two bytes in the buffer and be shifting a 3rd one into the receive shift register at the same time. Overrun does not occur unless the stop bit of the 3rd byte is received without the buffer being read at least once.
Assuming you're communicating at the standard 9600bps and 8N1 format (8 data bits, No parity, 1 stop bit), each received byte would have a total of 10 bits (1 start, 8 data, 1 stop) and would be received at a rate of 1.04mS per byte ((1 / 9600bps) * 10 bits = 1.04mS per byte).
This means that it would take 3.12mS for 3 bytes to shift in and cause buffer overrun. The EEPROM read/write cycles happen much faster than this (within microseconds). Unless your data rate is some really high number, it should be safe to disable interrupts temporarily while executing an EEPROM read/write even with continuous serial data. If one byte gets received during the read/write operation, the PC will immediately jump to the receive interrupt handler upon re-enabling interrupts.