Eagle Pro: Design rule check is absolutely cluttered with fine pitch IC clearance problems..?

[Flyback]

Hello,
I have layed out a board in Eagle pro, and wish to run a design rule check so as to ensure that different-net copper tracks/pads are more than 0.3mm apart from each other. The problem is that the microcontroller and opamps, and the pwm controller ICs have pad to pad clearances of just 0.2mm since they are very fine pitch components. How do I run the design rule check so that it ignores the pad to pad spacings, but still checks the track to track spacings elsewhere on the board?
At the moment, the design rule check is absolutely cluttered with clearance violations in and around the fine pitch ICs. Can I run a design rule check on for example a restricted highlighted area of the board, ie an area on which there are no fine pitch ICs.?
Please find the board file attached. Eagle from cadsoft.de has a free viewer, available on their website

 

[jpanhalt]

0.3mm is almost 12 mil. Why do you want such wide separation? Have you tried 6 mil (0.15 mm), at least for pads? You also have errors that are not due to the fine pitched IC's, such as this:

That looks like a routing error where you overlapped tracks. There is no clearance that will cure that. I would fix those errors first, then address any remaining IC-related errors.

John

 

[Flyback]

thanks, the error you depict is unavoidable for me because I use home -made net ties, to tie together nets of different names, which are however, shorted together.
I prefer to have separation 0.3mm rather than 0.15mm if I can...you never know when youre going to get that breach in the solder resist and youd then prefer a wider spacing.

 

[jpanhalt]

Obviously 0.3 mm pad clearance will give clearance problems with your devices, since the IC pitch is smaller. One thing you might consider to help weed through the >1000 errors is to do the DRC section by section. On the DRC dialog, press "select", then either select a component (be sure origins are visible) or outline an area, and DRC will be done only for that. It will be tedious.

If your concern about solder bridging is that important, then why use components that have such fine pitches?

John

 

[Flyback]

I had to use small fine pitch components because they were all that I could fit on the pcb size that I was restricted to.

 

[ronsimpson]

I can see you have put 1000s of hours in this project.

I redid net N$29 in just a couple of mouse clicks.

Using a simple polygon:

Set: Layer = top, width= something very small
There is a small window at the top where you can type in commands: POLYGON N$29
Draw a rectangle. It should be red dotted lines. The click on RATSNEST button.
The polygon bled into net N$26. (not good) So INFO button. Clock on the edge of the polygon you drew. Down to PROPERTIES. Un-select THERMALS, and set RANK=6.
>>The RANK=6 means that all other POLYGONS will cut into it.

What I often do is make a GROUND polygon that covers the entire board on one or more layers. Rank=6, and thermals=off.
Then make some small power polygons with a rank of 5. Then some wide areas for high current with a rank of 3.
Now lay down the traces that will eat their way through the polygons.

 

[ronsimpson]

I see that you have many cases where there are traces on 2 or 3 layers doing the same job. (that is OK, even good)
If you make a polygon on layer 1, you can copy it and change the layer number on the new copy to get two (or more) exact copies.

 

[ronsimpson]

As long as I am talking about polygons:
Here is the polygon. In this mode you can see through it.
Note I plowed though other polygon. I also went out to the edge of the board.

Now I pushed the RATSNEST button.
Note the copper does not go to the edge of the board and the other polygon cuts into this polygon.
NOW THE REAL QUESTION: How do you get back to the "clear" looking polygon? You might need to see through the polygon to rout traces.
ANSWER: I don't know how. There must be a easy way. I pick up a side or corner of the polygon and move it a small amount and then move it back. Any change will cause it to go clear.

This is what it looks like with THERMALS turned on. I do not do this. I am trying to get the heat from these parts to travel into the copper and be carried away. With the way I solder the parts the thermals do not help.

In some cases you want thermals on for all the little parts but you do not want thermals for the hot transistors and ICs.
Make a polygon with thermals on for the entire area or board. Then make small polygons (the size of the IC or transistor) with the thermal turned off. It is OK to have polygons on top of polygons. By stacking polygons you can have small areas with different effects. (thermals, clearance, line widths, etc)