dv/dt for a MOSFET

[smanches]

I'm trying to clarify something.

In a mosfet, it is bad for Vds to rise too quickly; this is what the dv/dt parameter is for. In this particular case I'm looking at this mosfet https://www.st.com/stonline/stappl/productcatalog/app?path=/comp/stcom/PcStComOnLineQuery.showresult&querytype=type=product$$view=table$$orderable=yes&querycriteria=RNP139=1167$$rpncode=220805 which has a dv/dt of 45V/ns. However, when you apply your main power to your circuit, is it just the intrinsic impedance of the circuit that usually prevents it from rising too fast?

I'm sure the input capacitance, snubber capacitance, etc would decrease the dv/dt. But is that all? Am I missing something?

 

[BrownOut]

You may allow VDSto rise just as quickly as it will with no damage to the MOSFET. What dV//dT spec are you talking about? I only see something related to the reverse recovery of the protection diode.

EDIT: OK, I see what you're talking about. That's just a spec giving switching characteristics. It's nothing to worry about.

 

[crutschow]

If you notice note 1 for that parameter under Table 5 refers to turn-off of an inductive load.

It's not a limit and it has nothing to do with the power turn on to the transistor (which likely would have a much slower risetime due to intrinsic stray impedances, as you noted.)

 

[smanches]

Oh, so the Drain-source dv/dt could come into play if your switching rise time is too fast? Not the actual dv/dt to the drain itself?

EDIT: Wait, I have a discrepanecy in another doc. ...

https://www.electro-tech-online.com/custompdfs/2010/01/AN-9010.pdf

It's on page 27.

EDIT2: I guess it's not a discrepancy, just doesn't mention inductive loads at all. Is it that an inductive load is the only thing that could make dv/dt rise fast enough?

 

[crutschow]

Inductive loads are the most likely to generate a high dv/dt. Of course, even simple circuits have some small inductance so a high dv/dt could occur for just about any circuit. It's mainly determined by the inductance to capacitance ratio.

 

[Sceadwian]

smaches, from what I know of it it can't occur during turn on, only turn off because of the various charged states of the junctions in a Mosfet during forward conduction. If when switched off the D/S voltage changes dramatically in a reverse fashion the charge carriers caught inside the MOSFET body will cause the parasitic BJT (built into every mosfet by it's structure) to actually manifest itself noticeble, the effect being the FET can't be turned off again, devices usually turns to smoke at that point. I think it's influenced by the forward current during the switching event, could be wrong never studied the phenomom, as modern power mosfets body diodes generally take care of things just fine. You can always add a little capactance or additional snubber diodes to prevent the DV/DT spike from occuring.

 

[Roff]

If dv/dt is high, and gate drive impedance in the low state is sufficiently high, the C*dv/dt current through Cdg can raise the gate voltage well above V(th). This will turn on the channel while the drain voltage is high and a lot of current is available (as in from an inductive load that has just been switched off). This combination of high Vds and high Ids can damage the MOSFET.

 

[smanches]

So my other question in relation to this is how fast can voltage rise in an inductor when powered off? That is, if there was no protection diode, and the back emf voltage has to rise, how fast does it rise?

 

[crutschow]

So my other question in relation to this is how fast can voltage rise in an inductor when powered off? That is, if there was no protection diode, and the back emf voltage has to rise, how fast does it rise?

It's determined by the value of the inductance and (stray) capacitance in the circuit. When you turn off the transistor this LC circuit starts resonating. The risetime is equal to 1/4 cycle of the LC resonant frequency. For example, if the LC resonant frequency was 1MHz, then the risetime would be 250ns.

Edit: The risetime I'm referring to is the time from 0V to the peak voltage and looks like 1/4 of a sinewave. Thus it's not the typical 10%-90% risetime value that is mentioned in digital circuits, or the one-time-constant risetime of 0-63% in RC circuits.

 

[smanches]

Interesting. I would never have been able to figure that out. Thank you!

The pieces are coming together.

EDIT: So that means smaller inductance will rise faster, but a higher inductance will have more power, with the same stray capacitance.

 

[crutschow]

EDIT: So that means smaller inductance will rise faster, but a higher inductance will have more power, with the same stray capacitance.

Yes. Thus a larger inductance will generate a higher peak voltage also.

 

[Sceadwian]

EDIT: So that means smaller inductance will rise faster, but a higher inductance will have more power, with the same stray capacitance.

I think this actually depends on the Q value of the inductor not just its Henry value, although for a higher Henry value obviously higher energy states are available.
Small inductors being of high Q vs high value inductors being of a low Q is because of the general construction. Higher Q is bad for inductive kickback in every way, but generally desired for normal operation.

 

[Cubrilo]

Albeit the post is old, I find it very interesting, and I hope to revive it. The TS specifically asked for the first application of power, let's call it "inrush"

However, when you apply your main power to your circuit, is it just the intrinsic impedance of the circuit that usually prevents it from rising too fast?

Regarding quoted mosfet datasheet parameters: these are not a direct answer to your question:
dv/dt Peak diode recovery voltage slope is related to diode reverse recovery, i.e. the diode is already conducting when the dv/dt is applied
dv/dt Drain-source voltage slope may be related to Unclamped Inductive Switching, i.e. the mosfet is already conducting when the dv/dt is "applied". But I'm not sure about this because a condition is Id = 7 A, whereas Avalanche current is only 2.5 A?!

Unfortunately I don't know the direct answer to your question.

 

[ronv]

Albeit the post is old, I find it very interesting, and I hope to revive it. The TS specifically asked for the first application of power, let's call it "inrush"

Regarding quoted mosfet datasheet parameters: these are not a direct answer to your question:
dv/dt Peak diode recovery voltage slope is related to diode reverse recovery, i.e. the diode is already conducting when the dv/dt is applied
dv/dt Drain-source voltage slope may be related to Unclamped Inductive Switching, i.e. the mosfet is already conducting when the dv/dt is "applied". But I'm not sure about this because a condition is Id = 7 A, whereas Avalanche current is only 2.5 A?!

Unfortunately I don't know the direct answer to your question.

There is a good write up here on both diode and FET Dv/Dt.
Don't forget there is a load between the supply and the FET when power is applied.
https://www.fairchildsemi.com/application-notes/AN/AN-9010.pdf

 

[MrAl]

Hello there,

There is a fairly simple concept behind the dv/dt.

The main concern is the unwanted turn on of the MOSFET when a ramp voltage is applied to the drain source of the device, and this happens with some loads when the MOSFET turns off.

In other words, if the dv/dt ramp is too steep, the MOSFET turns 'on' when it is supposed to be 'off', and since there could be high voltage on the drain the MOSFET could be destroyed.

That is really all we need to know, but in case you are wondering how this happens, there are two mechanisms that act to cause this unwanted turn on:
1. The drain to gate capacitance causes a high current to flow from the drain into the gate, which if high enough, will turn the MOSFET on. The steeper the ramp, the higher the current.
2. The parasitic 'bipolar' transistor from drain to source. The collector base capacitance conducts just like in the MOSFET with a steep ramp, and that capacitance turns this transistor on and again high current may flow and destroy the MOSFET.

Another problem that can result is very bad oscillation where the MOSFET turns on and off several times which acts to modulate the ramp, and the repeated on and off causes very high power dissipation in the MOSFET so it burns up.