Dual 4 input NOR gate transition time

[QiQ]

Hi all, first post here.

I'm using a 4002 (dual 4 inputs) IC to trig an interlock mechanism on a power source. Although the transition 5 to 0V is instantaneous, I was wondering why the recovery back to 5V takes so long (like 7-8 seconds with a sine behaviour). Is that normal?

 

[MikeMl]

No.

What kind of load is the gate output driving?

 

[QiQ]

No.

What kind of load is the gate output driving?

None for the moment. I was just testing the chip itself with a scope. Once the whole circuit is ready, I'll put a buffer that trigs a relay (either an op-amp folower or a buffer that I have yet to find). Better ideas are welcome.

 

[MikeMl]

Then I think you have a defective gate with a blown pullup transistor. Assuming that the inputs are driven or tied to clean logic levels, then the rise/fall times should be roughly equal. Are any of the inputs "floating"?

 

[QiQ]

It's a dual 4 input, so initially, I had only fully connected one of the two gates. Afterwards I grounded all inputs of the second gate to see if it would make a difference. There are still 2 NC floating pins.

I bought 5 of them and tested 3 with the same behavior. The other 2 I assumed would act the same.

 

[crutschow]

Are you using 5V for both signal and power? What is your signal source?

 

[QiQ]

Yes. The exact same 5 volts for power and signal... come to think of it, that could be a problem right? Then again maybe not.

 

[MikeMl]

Try this: on one 4-input NOR gate, tie three of the inputs to 0V. Tie Vdd to 5V. Tie Vss to 0V. Tie the four inputs to the other gate to 0V.

Drive the fourth input to the first gate alternatively to 0V or 5V while watching the output pin for that gate. The output should be 5V while the input is 0V and vice versa. The switching times up and down should be symmetrical.

 

[crutschow]

My question about the signal was, how are you generating the signal: signal generator, clip leads, ouija board? My point is, is the input signal being rapidly driven both high and low?

 

[QiQ]

I think that's exactly what I did, but I'll double check to make sure. I'll do a follow up tomorrow.

Thanks a lot for your help.

 

[crutschow]

I think that's exactly what I did, but I'll double check to make sure. I'll do a follow up tomorrow.

But you haven't said exactly what you did. Is it hard to explain?

 

[QiQ]

But you haven't said exactly what you did. Is it hard to explain?

Sorry. I hadn't read your reply in time. I was answering MikeMl's. I was using a steady 5 volt signal on one pin, the same used from the supply to power the chip, while the others were grounded.

PS: ouija board... that's humour right?

 

[crutschow]

Ok. You said you apply steady 5V to the input but how did you get 0V on the input? To get a fast transition logic 1 to 0 time by just touching the input with a clip-lead you will need to add a pull-down resistor to ground (say 1-10kΩ) and it doesn't sound like you have that. If the input is floating when you remove the 5V from the input, than the input is undefined and the output can be erratic. In your case it apparently slowly floats toward ground which would account for the slow output rise to 5V.

The rule with CMOS is: NEVER LEAVE AN INPUT FLOATING, unless you want random behavior from the chip. It's a simple rule but many working with CMOS seen not to know it.

Yes, the ouija comment was my attempt at a little humor.

 

[QiQ]

Yesterday I had a dream. In my dreams apparently, I am smarter than when awake. I spun the schematics of the chip in my head, with the pFETs and the nFETS and remembered that the "C" in CMOS stands for complementary... thus I came up with the answer you're giving me this morning, and that there is no way the complementary layer could've pulled up the output with a floating input.

Huge rookie mistake. Thank you guys. You had it right on.

 

[QiQ]

Another quick question...

Another of my preoccupations was what to chose to drive the relay that opens the interlock. I thought of using an opamp but I'd need something able to source roughly 100mA... any suggestions?

 

[MikeMl]

Logic gate driving the gate of a "Logic-Level MosFET". No opamp or driver required.

 

[QiQ]

Awsome. Thanks Milke.