double frequency of pwm signal

[frankske_]

Hi, I have a 5V pwm square wave that can vary from 1 to 200Hz.
I'm looking for a simple schematic to multiply the frequency by 2.
It's not a problem is duty cycle halfs by doing this. I have 50% and need 20% minimum, so it won't be a problem.

 

[Diver300]

Normally, when a signal is described as PWM, then the duty cycle is important, and the frequency is reasonably constant. However in your case it seems that the duty cycle doesn't matter, but the frequency changes a lot.

A simple frequency doubler would produce a pulse on the rising and faling edge of the signal. Something like **broken link removed** but you should use Schmitt trigger inputs. That would give the same pulse width at all frequencies so the duty cycle would be much less than 1% at low frequencies.

If you want to a constant mark-space ratio, you would need a significantly more complicated solution.

Can you say anything more about the application?

 

[jpanhalt]

Is this for a speedometer or like application? There have been similar projects here that used a frequency-to-voltage converter followed by a voltage-to-frequency converter (two chips). You can keep 50% duty cycle that way.

I just tried a search and get errors. It seems only to go back to January, 2012. I will try later and post an update, if possible.

Edit: Here are typical V-to-F and F-to-V chips that you might want to look at: NJM4151, KA331, XP4151. They are virtually identical.

John

 

[ronsimpson]

The F-to-V and V-toF is a cleaver idea. There will not be an exact 2x but a ratio that can be anything. 1.95x, 2.231x

A phase lock loop, such as a CD4046 will give you 2x (or 3x, 4x.....) at 50%. The 50% will be 50% and the multiplier will be exactly 2x. With the CD4046 an MC14046 there are options for the phase shift between input and output signals. (phase lock or edge lock)

 

[ronsimpson]

http://www.electronicecircuits.com/electronic-circuits/4046-ten-times-frequency-multiplier-circuit
Here is an example of a 10X with a range of 10hz to 10khz.

 

[jpanhalt]

Yes, you illustrate the exact reason I asked if it was for a speedometer. The earlier thread was on another forum (my memory error). A PLL was considered, but the real project was a speedometer problem. The author was changing tires, axle ratios, etc., so he needed something that was not an exact double.
John

 

[ronsimpson]

John, Then the F-V-F will work best. A little PIC10Fxxx will also do the job. Connect a pot to the PIC10Fxxx to adjust the ratio. That sounds like a fun little project.

 

[alec_t]

A phase lock loop, such as a CD4046 will give you 2x (or 3x, 4x.....) at 50%.

Can a PLL cope with a 200:1 input frequency range without having to change external components? I stand to be corrected, but I was under the impression that a PLL is normally expected to handle only a limited frequency range.

 

[jpanhalt]

Why don't we wait for one-post frankske_ to tell us what is he really trying to do before solving a problem that may not exist?

John

 

[ronsimpson]

It is hard to get any VCO to work over 200:1. The range of any PLL is based on the VCO. I have seen the 4046 work from 20 to 20k. I think that range is not good for a stable oscillator. A PLL has an error amplifier, so to speak, and its time constants become difficult over a wide range.

I brought up the CD4046 because the VCO has a 50% output.
The VCO has a capacitor and two resistors. One RC sets the lower frequency and RRC sets the upper frequency. It is pretty simple to set up the VCO.

One advantage is the CD4046 / MC14046 is that the upper and lower frequencies are fixed (by RRC) and the output will not get out of that range. That range is normally set small but does not have to be.

 

[misterT]

Use a low pass filter to filter the PWM signal. Then use a higher frequency triangle wave generator and a comparator to get high frequency PWM.

 

[ronsimpson]

MisterT,
You do know he wants this to work over a 200:1 frequency range.

 

[alec_t]

Looks like the OP has lost interest, but I amused myself by cobbling together a digital solution in LTSpice. Because of a lack of convenient 8-bit models I limited the sim to 4-bit. This limits the input frequency range to 7:1 but demonstrates the principle. To cover a 200:1 frequency range requires at least 8-bit parts.
Operation:-
An XOR gate is used to derive a pulse at each edge of the input signal. The pulse sets a S-R latch. A first binary counter is clocked by a free-running clock. The output (Q1) of the first stage of the counter clocks a second counter at half the free-running clock rate. Each input pulse edge resets both counters, but the resetting of the second counter is briefly delayed until after its count has been latched. The latched count is half the maximum count value in the first counter. A 4-bit magnitude comparator (no model available) made up of XNOR and AND gates detects when the running count in the first counter matches the latched count and the comparator output resets the S-R latch. The S-R latch output is a square wave at twice the frequency of the input signal and with a duty cycle which is ~ 30-60%, depending on the frequency ratio between the input signal and the free-running clock.

 

[misterT]

MisterT,
You do know he wants this to work over a 200:1 frequency range.

He does not know what he wants to work with He did not even tell us how dynamic the information carried in the signal is.