Double buffered data latch - parallel input

[atferrari]

In my design, every so many usec I output row/columns data (5 bytes x 8 bits ea) all at once. Up to now, I could go away with the 74HC595 serial shift register but since I need it to be faster, the time it takes to shift the 40 bits in and then show them all at once is more than what is available for each "frame".

Thinking of doing something similar with parallel input data latches strobing the 5-bytes output at once, I could not find an IC able to keep the previous value at the output UNTIL the 5 new ones are sequentially loaded.

Checked the 74HC373, 374, 573, 574 variations but they all lack an intermediate register that would allow the succesive input of bytes while the previous data is still shown.

Any chip that I could have overlooked and is easily available? Even browsing the long list in the data books in paper in my library I couldn't find one.

 

[geko]

74HC594 is serial in parallel out with separate shift and latch clocks

**broken link removed**

 

[atferrari]

Parallel input requested, as I said.

 

[ronsimpson]

Take 8 of the HC595s and drive them from your parallel port. (8 bits/byte) so you have 8 parallel in and 8X8 out.

 

[dougy83]

You can do it with ten 74HC574 ICs. The first five make up the parallel shift register, while the the other five are used as the output latch.

The interface is: an 8-bit data input, single data shift clock, single output latch, and 40-bit data output.

 

[atferrari]

Replies here and in another forums seem to confirm that there is not a commonly available IC doing what I need.

My problem is that the overhead, running my micro at the maximum clock of 32 MHz, is currently two orders of magnitude higher than the available frame time slot.

If later, I decide to increase the row/column data to 8x8 (64 bits) it would become even more unmanageable. That's why I wanted it double buffered parallel input. Duplicating the numbers of ICs, 8 to 16, seems too much.

 

[dougy83]

Well you can just use the five (or eight) 74HC595 in parallel then. The SIPO inputs go to each of the five or eight outputs from the microcontroller; clocks are commoned, latches are commoned.

If you go for eight SIPOs, you can load the 40 bits in five clock pulses. If you use five SIPOs, you can load the 40 bits in eight clock pulses.

For 64 bits, obviously it will take eight clock pulses and eight SIPOs.

EDIT: Oh, ronsimpson already suggested this above...

 

[kubeek]

Why not use two normal edge triggered latches and invert clk on one of them ? This will make a double buffer like you wanted, and it will be controlled by a single wire which is easier on the software.

 

[ronsimpson]

This is a job or a CPLD or FPGA.

 

[atferrari]

Why not use two normal edge triggered latches and invert clk on one of them ? This will make a double buffer like you wanted, and it will be controlled by a single wire which is easier on the software.

Could you please elaborate?Two octal latches per byte, you mean?

 

[atferrari]

This is a job or a CPLD or FPGA.

Wish I knew to work with them.

 

[ronsimpson]

Your project is probably too big for a CPLD and too small for FPGA. Either will work, it is in that in between area.

Xilinx has a development system free. It can be driven by schematic. They have building blocks like 8DFF which is much like the 8 bit data latches you know.
Take 5 of the 8 bit DFF and connect them to 80 I/O pins. The clock is the "clock output" pin.
I would take 5 of the same 8 bit DFF and make a 8wide x 5 deep shift register.
Inputs (D0-D7), clk
Outputs: D0-D79 goes to the output latches.

The schematic will have D0-D7, DataInClock, DataOutClock as inputs and D0-D78 as outputs.
That is a simple project and good for your first.

This will use up about 1/2 of Xilinx's smallest part.

 

[atferrari]

Just to say I am rethinking the whole thing. I was suggested to use SPI, something that I overlooked in the beginning. Shame on me!

Gracias again and ¡Feliz Año Nuevo!