Dmips

Hello guys,

I'm studying the ARM Cortex M0 and had a general question about MIPS. So you can have the M0 in 180nm and 65nm, why is the DMIPS the same?

I you have a lower semiconductor process, than the transistors lay closer towards each other so less delay and the taks is done earlier. DMIPS states the number (in million) of tasks completed in a second. So why isnt the DMIPS for 65nm bigger than 180nm?

Hopefully someone could help me out on this one.

The M0 core isn't intended to be a computational powerhouse. It's designed to be power efficient and inexpensive. If they keep the clock the same after a die shrink, overall power usage is lowered which is what's desirable in the market the M0 is targeted towards.

There are a lot of other factors playing a role here that could have been design tradeoffs or specific product engineering decisions. It's possible the underlying architecture can't handle higher frequencies, the memory might not be able to handle higher speeds, power draw might increase unacceptably with higher frequencies, attached peripherals may not work properly at higher frequencies, etc., etc.

Is the 65nm one able to run at higher clock frequency than the 180nm one? If yes, then there is something fishy.
If not, then you´re asking the wrong question.

Here's the flyer :https://www.electro-tech-online.com/custompdfs/2012/10/CortexM0-flyer.pdf, stated on page 3. I think its able to run at higher frequencies to to the lower delay.

Well, read that table in the datasheet carefully again, and point your finger exactly where you see DMIPS of the two cores.
As far as I can see, there are two sets of numbers, one states 0.90 DMIPS per megahertz, and the other states 10 and 75 DMIPS per mW.
Instructions per second per megahertz depends only on the architecture, it is basically a number that tells you that this core can on average do 0.9 instructions in one clock cycle. In other words, if you run the processor at 1MHz you get (on average) 900,000 double precision instructions executed in one second.
The second set of numbers is self explanatory.

The total DMIPS depends on DMIPS per MHz times the actual operating frequency. And since the smaller core can run at over five times the frequency of the older technology, you get over five times the DMIPS.

You are right that in smaller technology the core has smaller delay. But smaller delay implies higher operating freqency and thus is not directly responsible for increasing DMIPS, it does it through allowing faster clock.

Ok kubeek, thanks for the information. But can you tell me why the operations have to be double precision ( to write 32 bits to a register?)?

And the gate count, does this reflect the number of semiconductors used to store the bit values?

Appreciated !

They don´t have to be double precision, but beacuse for mp3 and video you generally do the calculations in floating point, a designer wants to hear the performance of that. Also the performance in integer will be comparable or a little better.

Lower gate count (think of logic gates) means it has simpler core and uses less power than some other more complex design. It has nothing to do with ? storing bit values?, whatever that may mean.

kubeek said:

Lower gate count (think of logic gates) means it has simpler core and uses less power than some other more complex design. It has nothing to do with ? storing bit values?, whatever that may mean.

Click to expand...

Aha ok, now I get it. And the gates serve to do like algorithmic stuff and so on.