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Dissipation in sync FET due to reverse recovery in sync Buck converter?

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Flyback

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We are using the IRF6648 FET as a sync FET in a sync buck with vin=28v vout=1.5v, iout=17.1A, fsw=200khz.

The Qrr for IRF6648 is 56nC.
Therefore the dissipation in the lower FET due to this Qrr is ..
(Qrr * Vin * Fsw)/2
Thus equals 0.155W

However, the datasheet conditions for Qrr measurement involved a di/dt of 100A/us.

In our sync Buck converter the di/dt would be about 17.1A/8ns which equals 2137A/us.
Given this difference, how much more would the FET dissipation be due to this reverse recovery?

IRF6648 FET datasheet
http://www.infineon.com/dgdl/irf6648pbf.pdf?fileId=5546d462533600a4015355ec6e561a59

PS: There's little point in using a schottky in parallel with the sync fet because sufficiently voltage derated schottkys for such purpose have high vf and would not sufficiently stop the intrinsic fet diode from conducting. -The intrisic fet diode would still conduct very significantly even with a paralleled schottky.
 

crutschow

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I would not think that reverse recovery charge would vary significantly with di/dt and thus neither would the dissipation.
 

ronsimpson

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When the MOSFET is on there is about -0.1 volts across it.
Usually there is a time after this FET is off and before the top FET is on. Is the D-S voltage -1 volts?
Do you have pictures?
 

Flyback

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Thanks...
The following article, in the “conclusion” on page A-32 states that a higher di/dt actually reduces overall turn-on switching losses….Page A-30 details the reasons why….

Switching losses in MOSFETs:
https://www.fairchildsemi.com/techn...covery-and-Its-Effect-on-Switching-Losses.pdf

..this is quite interesting, because for example in Boost PFC stages in CCM, its well known that if using ultra-fast diodes for the boost diode, then it is crucial to reduce the di/dt in the diode at FET_turn-on (by slowing up the FET turn-on by using a high value series gate resistor) in order to reduce the losses in the FET due to the reverse recovering diode. So why the above article comes up with a different conclusion is interesting. Violent Reverse recovery in boost pfc diodes by having too high di/dt in the diode is known to be a “killer” for the boost PFC converter.

Usually there is a time after this FET is off and before the top FET is on. Is the D-S voltage -1 volts?
Yes , due to the delay that you spoke of, the sync fet's intrinsic diode is definetely conducting when the top fet of the sync boost turns on...(so yes the switching node is at about -1V)
 

ronsimpson

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(so yes the switching node is at about -1V)
Then you are using the internal diode which has a forward voltage of about 1 volt. and Has a 30nS rr at 100A/us.
While I don't know if a paralleled Schottky will help it is worth a try. The Schottky will not do anything during the 0.1V turn on time but during the 1.0V time I think it might help. Keep the leads short.
 

ronsimpson

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Got an idea for you if you want to fight this problem.

Back when PFC was experimental....and soft recovery diodes were not available.....I fought ff current in a big way. With 400 volts of supply, it was hard to find a good diode for the job.

So one of the things I played with was to limit the current on the MOSFET during the rr time. (FET + Diode)
I added a source resistor+inductor (bead). In your case the top FET, not the bottom one.
In your case you need 14A to lift the inductor and lets say 14 more amps to fight the diode. =28A
Use a source resistor sized so it will limit the current to 28A.
....Gate drive =10V, 4V gate turn on voltage, so at current limit there could be 6 volts on the source resistor.
The bead saturates out after 30nS*6V so it shorts out the resistor and removes the current limit function.
I know they say to never put inductance in the source but.....
upload_2016-6-5_21-59-53.png
 
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