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Digital logic circuit not able to understand the operation

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Nathaniyelu

New Member
Hi everyone,
This is Nathaniyelu.
I have attached a file to this thread.
Please go through..
Iam not able to understand the in depth operation of this circuit..
74LS123-Retriggerable Monostable multivibrator.
74LS73-JK flip flops with clear presets..
8038-sine wave generating I.c.
AD713-...?

Inputs to the circuit are:
1.clock.
2.NRZ signal..and a
3.Tone signal (some KHz sine wave).

Out put will be an fsk signal..PCM Coded...

Please help me..
Thanks in advance...
 

Tony Stewart

Well-Known Member
Most Helpful Member
NRZ data and clock are assumed synchronous inputs
Clock is converted to a fixed small duty cycle by unorthodox means.

This translates to a avg DC voltage to modulate VCO ICL8038.
This avg DC "should be a LPF output of XOR gate is inverted by NRZ input to drive VCO.
Instead adjust pot and driving VCO with phase complemented clock is integrated by VCO.

Not very precise way to create FSK. It might work in theory, but not very well.
A more precise way would use PLL with variable divider or precise linear VCO with gain offset on NRZ input.
 

Nathaniyelu

New Member
Dear bro Tony,
Thanks for your kind reply,
Especially I want to know the operation of monostable multi vibrator and jk flip flops..
Some body said to me jk flip flop act as a frequency divider(divide by2)..but divide by two means j,k should be at high..but in our circuit it is not like that..j is held at high,k is held at low and clear s held top one at low..bottom one at high(I think)..??
Could you please explain in detail..?
 

kubeek

Well-Known Member
Most Helpful Member
JK flip flop acts almost the same as a clocked RS flip flop, except for the case where J=1 and K=1, but in this circuit K is conneted to 0 so it cannot happen.

In fact this circuit acts as a flip flop with synchronous set and asynchronous reset.
 
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