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What's the difference between JK, D flipflop......
And what is asynchronous preset and clear......
What is a level triggered and pulse triggered?
Pls advise.
I described a JK in a previous post including asynchronous preset and clear. Do a search of my posts.
A D type has only one synchrouous input (D) in lieu of 2 (J & K)
When the clock signal goes from Low to High (if positive edge trigger) the Q output is set equal to the D input. For a Flip Flop with negative edge trigger, the change occurs on the High to Low transition.
I have not heard of the terms "level triggered" and "pulse triggered"
I assume they refer to the way the FF is set or reset. So I assume that "level triggered" refers to the asynchronous inputs which cause the FF to be set or reset by the application of the correct voltage level on the Preset or Clear inputs. I would not use the word "triggered" in this case.
And I assume that "pulse triggered" is what I would call "edge triggered", ie. the FF changes state on clock signal transitions as I described above.
I don't understand your first question. What does "yr title" mean?
A master/Slave FF is 2 FFs in one. The master is set initially and then the slave is set according to the master. I'll give you more detail tomorrow. I'm short on time now.
Some FF setups respond better to a Single Pulse Clock.
Level triggered means that. Triggered at a Logic 0 or triggered at a logic 1. Example: if a device is triggered by a logic 1 it will trigger at the peak of the logic form, then untrigger so to speak at the decend of the logic form, so it will trigger then fall back to previous state where as a Edge trigger device is only triggered at the rise or the fall of the clock and not both.
Asynch and PS and clear basically means you can input a logic command without a clock. Preset a number (logic) or Clear (logic)> you can PS a logic 1 or a logic 0 and Clear is most times Logic 0 on the output.
So if you set up a keypad and press numbers for a latching circuit, you can clear it at anytime with the CLR async input
Master-slave flip-flops aren't used much anymore. Basically, they were two flip-flops chained together to eliminate some of the timing issues. I couldn't tell ya how they worked, since my text doesn't cover more than that.
Master slave FFs. When the clock signal goes High, the state of the J and K inputs cause the master to be set (or reset) or not altered depending on the J and K states.
When the clock signal goes Low, the slave is set according to the state of the master and at that point tne Q and Q bar outputs change (if they are to change).
My recollection (its a long time ago since I studied M/S FFs) is that the "ones and zeros catching" refers to the fact that if QN is High, the J gate is open. If C is High, a brief High pulse on J will set the Master FF. So when the Clock goes Low, Q will go High. So ones are "caught" by the master. The same applies to brief Highs on K if Q is High. I assume tis is what they mean by "catching zeros".
Whereas, with an edge triggered FF, the states of J & K are only sampled at the clock transistion. Thus a brief pulse on J or K between clock transitions will not be "caught".
If you understand tha above, you should be able to draw the waveforms.
As I said before, the term "level triggered" is not a term I would use. It is ambiguous.
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