It migth be stupid...
I'm trying to make a 8 bit logical comparator in VHDL, but ISE (from Xilinx) keeps on giving me messages like
WARNING:Cpld:1007 - Removing unused input(s) 'CLK'. The input(s) are unused
after optimization. Please verify functionality via simulation.
The global sketch is something like
Very simple as you can see...
But ISe keeps on giving me those messages for ALL in signals...
any help?
thanks.
I'm trying to make a 8 bit logical comparator in VHDL, but ISE (from Xilinx) keeps on giving me messages like
WARNING:Cpld:1007 - Removing unused input(s) 'CLK'. The input(s) are unused
after optimization. Please verify functionality via simulation.
The global sketch is something like
Code:
entity Comp is
Port ( LBus : in std_logic_vector(7 downto 0);
Trigger : in std_logic_vector(7 downto 0);
Mask : in std_logic_vector(7 downto 0);
CLK : in std_logic;
Eqin : in std_logic;
Eqout : out std_logic);
end Comp;
architecture Comp_Arch of Comp is
begin
PROCESS (CLK)
BEGIN
IF Eqin = '0' THEN
IF CLK'event AND CLK = '1' THEN
If LBus = Trigger THEN Eqout <= '1';END IF;
END IF;
END IF;
END PROCESS;
end Comp_Arch;
Very simple as you can see...
But ISe keeps on giving me those messages for ALL in signals...
any help?
thanks.