entity Logic is
Port ( LBus : in std_logic_vector(7 downto 0);
Serin : in std_logic;
CLK : in std_logic;
CLK_ser : in std_logic;
Addr: out std_logic_vector(15 downto 0));
end Logic;
architecture Logic_Arch of Logic is
COMPONENT Shift_Reg
Port ( CLK : in std_logic;
SERIN : in std_logic;
QTRIGGER : out std_logic_vector(7 downto 0);
QMASK : out std_logic_vector(7 downto 0);
QMODE : out std_logic);
END COMPONENT;
COMPONENT Comp
Port ( LBus : in std_logic_vector(7 downto 0);
Trigger : in std_logic_vector(7 downto 0);
Mask : in std_logic_vector(7 downto 0);
CLK : in std_logic;
Eqin : in std_logic;
Eqout : out std_logic);
END COMPONENT;
COMPONENT Contador
generic(n: natural :=16);
Port ( CLK : in std_logic;
CLEAR : in std_logic;
CE : in std_logic;
CE2: in std_logic;
Q : out std_logic_vector(15 downto 0);
ENDCOUNT : out std_logic);
END COMPONENT;
FOR ALL:Contador USE ENTITY Contador(Contador_arq);
FOR ALL:comp USE ENTITY Comp(Comp_arch);
FOR ALL:shift_reg USE ENTITY shift_reg(shift_reg_arch);
SIGNAL CLEAR, CE, CE2, ENDCOUNT: std_logic;
SIGNAL Triggout, Maskout, LogicBus: std_logic_vector(7 downto 0);
SIGNAL Eqin, Eqout: std_logic;
SIGNAL Q: std_logic;
begin
Compa: Comp PORT MAP(LBus, Triggout, Maskout, CLK, Eqin, Eqout);
Count: Contador PORT MAP(CLK, CLEAR, CE, CE2, Addr, ENDCOUNT);
Shift: Shift_reg PORT MAP(CLK_ser, SerIn, Triggout, Maskout, Q);
end Logic_Arch;