Design of double tail comparator

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gowri sankar said:
Design of double tail comparator for simulation in lt spice using 180 nm cmos technology
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Do you have an LTSpice library for the 180nm CMOS process? If so, post a link to it...

What is a double tail comparitor? Post a schematic or a link to an explanation of what it does.
 
Sir,
I am doing a project for simulation of double tail comparator using 180 nm cmos technology.My tool is lt spice .Now i am stuck at the design details of double tail comparator.Hope you can help sir.
 
Again, describe what a double tail comparator is. That is not an industry standard term.

ak
 
AnalogKid said:
Again, describe what a double tail comparator is. That is not an industry standard term.

ak
Click to expand...

And you need to know the specifications of the N and P channel transistors, the diffusion resistances and capacitances, the parasitic capacitances for the various layers specific CMOS process you are designing for. Those details are usually modeled in a simulation library (in this case, specific to LTSpice). If you do not have a pre-made library to install into LTSpice, your job will be much harder...
 
gowri sankar said:
Sir, this is the circuit we are working on.I do not know how to set w and l ratios for the transistor.so can you help me regarding the design of this circuit.
Click to expand...
Nobody knows this without having a set of process parameters for the 180 nm cmos technology.
 
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