Dealing with Signal connected to multiple drivers in Verilog

Hi,

I am using an FPGA to control a piece of scientific equipment, but am new to Verilog.

I have a counter on the FPGA, whose count is output to some pins. I want to have 2 trigger pins: a pos-edge on one pin advances the count, and a pos-edge on the other resets the count to zero. My code looks something like:

always @ posedge zbus[1]
COUNT<=COUNT + 1;
end

but when I add the following
always @ posedge zbus[2]
count <=0;
end

the code fails with the error of "Multi-source in Unit <ramp> on signal <count<31>>; this signal is connected to multiple drivers.". Which I understand is from me reassigning count in both blocks.

My question is: How do I circumvent this and get the behavior I want?

Thank you,