DDR3 Clock Differential Impedance

[wuchy143]

I am trying to figure out what the differential impedance for a clock on DDR3 memory should be. The part number for the DDR3 I am referencing is W3J128M72G-1066PBI. It's a microsemi part with a 1066MB/s, so the clock is 533MHz.

Exactly how should I go about calculating this?

 

[dknguyen]

No. 32 of
https://www.nxp.com/files-static/32bit/doc/app_note/AN3940.pdf

Or Section 6.3.1.7 of
www.ti.com/lit/an/sprabi1c/sprabi1c.pdf

Is that what you are looking for?

 

[wuchy143]

Thank you.

Yes, what's interesting is the NXP recommendation is saying 75 to 95 ohm differential impedance. The TI says 100 ohm diff. imp.

I thought there would be a standard or something. Meaning, if you are using X speed use Y diff. impedance.

Sadly I'm a noob when it comes to high speed

 

[ronsimpson]

Meaning, if you are using X speed use Y diff. impedance.

The impedance of a transmission line (coax or PCB traces) should be some what independent of speed. Like watching TV on channel-2 or on channel-12; the transmission line is the same impedance.

 

[wuchy143]

Awesome, thanks, makes sense.

I'm looking at a designs board file and see that they did not match the length of the diff pair. There is a delta of 3 mils. For some reason I remember .001" difference in trace length will create a 1 nano second difference between the positive and negative signals. Is that right?

 

[ronsimpson]

For some reason I remember .001" difference in trace length will create a 1 nano second

I remember 1nS/foot.
0.9835 ft/nanosecond, or 11.8 in/nanosecond

 

[wuchy143]

I remember 1nS/foot.
0.9835 ft/nanosecond, or 11.8 in/nanosecond

ah hah! that's what it was. Thanks!