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DDR3 Clock Differential Impedance

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wuchy143

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I am trying to figure out what the differential impedance for a clock on DDR3 memory should be. The part number for the DDR3 I am referencing is W3J128M72G-1066PBI. It's a microsemi part with a 1066MB/s, so the clock is 533MHz.

Exactly how should I go about calculating this?
 

wuchy143

Member
Thank you.

Yes, what's interesting is the NXP recommendation is saying 75 to 95 ohm differential impedance. The TI says 100 ohm diff. imp.

I thought there would be a standard or something. Meaning, if you are using X speed use Y diff. impedance.

Sadly I'm a noob when it comes to high speed :banghead:
 

ronsimpson

Well-Known Member
Most Helpful Member
Meaning, if you are using X speed use Y diff. impedance.
The impedance of a transmission line (coax or PCB traces) should be some what independent of speed. Like watching TV on channel-2 or on channel-12; the transmission line is the same impedance.
 

wuchy143

Member
Awesome, thanks, makes sense.

I'm looking at a designs board file and see that they did not match the length of the diff pair. There is a delta of 3 mils. For some reason I remember .001" difference in trace length will create a 1 nano second difference between the positive and negative signals. Is that right?
 
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