To be a bit pedantic;
you use the term 'D latch'.
You use the pin identification as EN; for the 'D' latch, this pin is the clock signal (CP).
Whatever data is existing on the 'D' input will be transferred to the 'Q' output on the RISING edge of the CP.
For the second pulse in your diagram, the GREEN input rises AFTER the CP(your EN) goes high; so the second RED pulse is not generated. Another way of saying this is that when the second CP (your EN) goes high, the state of the D input is low, so this level is transferred to the Q output. Also, for the first pulse, the RED stays HIGH until the NEXT positive going transition of CP (your EN). The first RED pulse does NOT fall to zero when the first green pulse falls to zero. This is because the D latch is a latch. But the first blue/green transition is correct.
Hope this helps.