D/A output buffer with variable gain (Vpp=0..20V)

[klausbock]

Hey there people!

As part of my studies, I've been assigned to design and build a Direct Digital Synthesizer (DDS) with a variable output amplitude. So far I've completed the DDS circuit (in a flex10k CPLD) plus D/A-Converter with all the additional features that are required by the assignment (Waveform selection, external trigger for freq-sweep, etc).

Whatsoever, the critical specs are as follows:

1) fout = 0.1Hz .. 1 MHz (Adjustable by uController)
2) Vout = -10V..10V (Adjustable by uController)

I simulated and prototyped the DDS circuit and it should be able to do a least 16x oversampling -> 16 Mhz sample clock. Hence the nyquist-freq is at 8 Mhz, so I have a wider band for anti alias filtering.

But Since the system is supposed to generate not only sine, but also square/sawtooth/triangle I would like the output-stage to have a bandwidth of > 1 Mhz. I will probably use a 4th order Bessel lowpass with the cutoff at 2Mhz. (3 octaves at -(4*6)dB/octave -> -72 dB at 16Mhz. Correct?)

Alas, I don't find any OpAmps that meet both the voltage (+-10V) and the bandwidth (>10Mhz) requirements - preferably dual supply and in a DIP package ;-). Not to mention the variable gain.

So, could anyone give me some hints on how to solve this "little" problem? Or assure that this specs are not feasable? Partnumber? Advise? Link? Something?

--
regards Stefan

 

[Hero999]

Please post what you hva already done.

If it's supposed to be 16x oversampling then if the maximum frequency is 1Mz it should be 32MHz shouldn't it? The minimum sample rate is twice the maximum frequency of interest and over sampling is any sampling on top of this.

 

[klausbock]

Thanks for your reply.

You are right, I misused the term "oversampling". What I meant was, that the DDS circuit is able to sample at 16 MHz (according to timing analysis and post-sythesis simulation. The D/A-output looks fine on an oscilloscope). It will be only 8x oversampling.

And, well, so far I only have this:

1. A DDS circuit on a Flex10k CPLD on an custom made evaluation board
2. A 12-Bit D/A (Intersil, HI5731BIPZ if that matters) connected to the board

The DDS has only a 10-Bit output but the 12 Bit DAC was the only fast one in a DIP package, that I could find.

Frankly, that's all I have so far.... the digital part. Things I have not or would like to know how/whether they can be done:

1. Digitally adjustable output gain/attenuation, so the amplitude is variable between 0V and 10V.
(Use a opamp with digital potentiometer? How best to implement a variable output amplitude?)
2. Preservation of signal wave form, as good as possible
(How to filter the D/A output? What are reasonable bandwidth requirements of the output buffer/amplifier/attenuation? Should I try hard to increase sample rate?)

I appreciate any advise.