Thanks for your reply.
You are right, I misused the term "oversampling". What I meant was, that the DDS circuit is able to sample at 16 MHz (according to timing analysis and post-sythesis simulation. The D/A-output looks fine on an oscilloscope). It will be only 8x oversampling.
And, well, so far I only have this:
1. A DDS circuit on a Flex10k CPLD on an custom made evaluation board
2. A 12-Bit D/A (Intersil, HI5731BIPZ if that matters) connected to the board
The DDS has only a 10-Bit output but the 12 Bit DAC was the only fast one in a DIP package, that I could find.
Frankly, that's all I have so far.... the digital part. Things I have not or would like to know how/whether they can be done:
1. Digitally adjustable output gain/attenuation, so the amplitude is variable between 0V and 10V.
(Use a opamp with digital potentiometer? How best to implement a variable output amplitude?)
2. Preservation of signal wave form, as good as possible
(How to filter the D/A output? What are reasonable bandwidth requirements of the output buffer/amplifier/attenuation? Should I try hard to increase sample rate?)
I appreciate any advise.