CPLD problem

Hi everybody,

I am now using a CPLD(EPM7064STC440-10) and I have a problem. I want to use the CPLD to control the pulse duration. The VHDL source code is like that:

architecture art of cpld_power is
signal counter:std_logic_vector(13 downto 0);
begin
-- counter process
process(counter,CLK,IO(1),ONTIME,OFFTIME)
begin
if(IO(1) = '0') then
counter <= "00000000000000";
elsif(counter = ONTIME + OFFTIME) then
counter <= "00000000000000";
elsif(CLK'event and CLK = '1') then
counter <= counter + 1;
end if;
end process;

-- output process
process(counter,CLK,IO(1),ONTIME,OFFTIME)
begin
if(IO(1) = '0') then
DRIVER1 <= '0';
elsif(counter < ONTIME) then
DRIVER1 <= '1';
else
DRIVER1 <= '0';
end if;
end process;

DRIVER2 <= '0';
end art;

when I do the functional simulation, the output waveform is correct, see Snap1.jpg. But when I do the timing simulation, there is something wrong in the output waveform, see Snap2.jpg. I have done some real experiment on it and it was really like the waveform in Snap2.jpg.

How can I fix the problem?

Thanks,
Samuel

can anybody help me?

solved

finally, i use a pwm controller and the problem is solved. the VHDL code:

pwm_fpga.vhd

Library IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE work.user_pkg.all;

ENTITY pwm_fpga IS
PORT(
clock, reset: in STD_LOGIC;
Data_value: in std_logic_vector(7 downto 0);
pwm: out STD_LOGIC
);
END pwm_fpga;

ARCHITECTURE arch_pwm OF pwm_fpga IS
SIGNAL reg_out: std_logic_vector(7 downto 0);
SIGNAL cnt_out_int: std_logic_vector(7 downto 0);
SIGNAL pwm_int, rco_int: std_logic;
BEGIN

-- store the 8 bit data value
PROCESS(clock, reg_out, reset)
BEGIN
IF(reset='1')THEN
reg_out<="00000000";
ELSIF(rising_edge(clock)) THEN
reg_out<=data_value;
END IF;
END PROCESS;


PROCESS(clock, cnt_out_int, rco_int, reg_out)
BEGIN
IF(rco_int='1') THEN
cnt_out_int<=reg_out;
ELSIF rising_edge(clock) THEN
IF(rco_int='0' and pwm_int='1' and cnt_out_int<"11111111") THEN
cnt_out_int<=INC(cnt_out_int);
ELSE
IF(rco_int='0' and pwm_int='0' and cnt_out_int>"00000000") THEN
cnt_out_int<=DEC(cnt_out_int);
END IF;
END IF;
END IF;
END PROCESS;

PROCESS(cnt_out_int, rco_int, clock, reset)

BEGIN
IF(reset='1') THEN
rco_int<='1';
ELSIF rising_edge(clock) THEN
IF((cnt_out_int="11111111") or (cnt_out_int="00000000")) THEN
rco_int<='1';
ELSE
rco_int<='0';
END IF;
END IF;
END PROCESS;

PROCESS(clock, rco_int, reset)
BEGIN
IF(reset='1') THEN
pwm_int<='0';
ELSIF rising_edge(rco_int) THEN
pwm_int<=NOT(pwm_int);
ELSE
pwm_int<=pwm_int;
END IF;
END PROCESS;

pwm<=not pwm_int;

END arch_pwm;


User_pkg_Inc_dec.vhd

-- INC & DEC function
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE user_pkg IS
function INC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function DEC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
END user_pkg;

PACKAGE BODY user_pkg IS

function INC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable XV: STD_LOGIC_VECTOR(X'LENGTH-1 downto 0);
begin
XV:=X;
for I in 0 to XV'HIGH LOOP
if XV(I)='0' then
XV(I):='1';
exit;
else
XV(I):='0';
end if;
end loop;

return XV;

end INC;

function DEC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable XV: STD_LOGIC_VECTOR(X'LENGTH-1 downto 0);
begin
XV:=X;
for I in 0 to XV'HIGH LOOP
if XV(I)='1' then
XV(I):='0';
exit;
else
XV(I):='1';
end if;
end loop;

return XV;

end DEC;

END user_pkg;

reference:
Pulse Width Modulation. ATMEL