Connecting two boards with flat ribbon cable

[TechnoGilles]

Hi all,

My project consists of two boards. On the master board, a PICMicro is used to communicate and control the slave board. On the slave board, a CPLD receives and answers communications from the master. Both the PICMicro and CPLD have strong output drivers that can sink/source more than 20mA.

Between the two boards is a 14 inch, 40 wire ribbon cable (an IDE cable for instance). The pinout and communication protocol is custom, but 8 of the wires form my data bus. Besides that are a few control lines and plenty of ground lines (12 to be precise).

On the slave board, the data bus feeds only the CPLD. On the master's side, the data bus is shared between the PICMicro and two other devices. So overall, 3 devices on the master board and 1 device on the slave board share the same data bus.

Communications on the data bus will happen at a rate around 10-15MHz.

What I would like to know is if I should take special care with my data bus because of the jump to the other board. If everything was local, I would simply connect the data bus to all devices and leave it floating (Hi-Z) when not in use. But since one of the device is on the other board, through that 14inch cable, should I do something special ? Special driver on either side ? Caps or series resistors ? Pull the bus high at all time ? Or low ? On which side ?

Tell me anything I should know !! Thanks !!

 

[TechnoGilles]

Here is a block diagram of my project.

 

[SABorn]

What is the bus, I2C?
If so you must have pullup resistors on the bus line anyway, normally around 4K7.

Most times these are located near the master and only 1 set are required.

A better discription of the slave devices might help answer your question further.

Pete.

 

[ronv]

Flat cables have a lot of capacitance between lines for high speed edges, so if possible run ground signal ground to avoid crosstalk.

 

[TechnoGilles]

SABorn : The slave device is a Xilinx CPLD with custom logic inside. As mentioned, the data bus is custom. It is 8 bit parallel. Along with it goes the control lines (/Reset, /RD, /WR, /IRQ, ACK, and the like).

ronv : Got it. I've already paired each data signal with a GND. And I also had room for 4 other GND that I distributed within the rest of the cable. Should I worry about that capacitace preventing me from reaching the 10-15 MHz range ?

 

[ronv]

No, I think you are ok if your drivers can drive 20ma. and are that fast to start with. Are the PIC outputs that fast?

 

[TechnoGilles]

I use a 30MIPS PIC. In some cases, I do a burst write in a series of 2 instructions that can thus reach 15 MHz. It's not sustained, obviously. For example :
// 4 byte burst
PORT is setup as output
PORT = data0 and /WR low
PORT = /WR high
PORT = data1 and /WR low
PORT = /WR high
PORT = data2 and /WR low
PORT = /WR high
PORT = data3 and /WR low
PORT = /WR high
PORT is back to HiZ (input)

Can the bus be left floating between the transactions or should it be pulled high/low on either side (master or slave) ?

Thanks !!

 

[KeepItSimpleStupid]

What specific chips are being considered for the driver and receiver?

Are you planning a differential driver/receiver system?

 

[ronv]

I would think the floating levels would be dagerous for the logic, so I would leave each bus in the inactive state (if possible). I have no science behind the next statement, but I would pull up the lines at the receiver end with something like the 4.7k mentioned above.
The capacitance (20pf) will slow the rise time about 5 ns which will leave you with about 25 ns of "good" logic levels at the receiver.
Obviously, shorter is better.

 

[TechnoGilles]

What specific chips are being considered for the driver and receiver?
Are you planning a differential driver/receiver system?

So far, nothing planned. Only the PIC on one side, directly connected to the CPLD on the other through the flat cable. Do I need something else ? What is a differential driver/receiver system ?

I would think the floating levels would be dagerous for the logic,

Hum. That makes me think... Does that mean that even locally, I should not let any bidirectional data line float when not used ? My control lines (/WR, /RD, etc), obviously, always have valid logic, but I usually let the data lines in HiZ when not used... Am I making a dumb mistake then ??