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I find it highly amusing to see syncronous counters in an asyncronous design.
To convert the divide by six into a divide by ten just change the preload on the first counter from the value "10" to the value "6". The count sequence will be:
Code:
6 7 8 9 10 11 12 13 14 15 6 7 ...
The way the second counter is set up it can only provide a divide by a power of 2.
HI and LO appear to represent logic 1 and logic 0 as you surmised.
Well you already have the first one by changing the preload value from "1010" = 10, to "0110" = 6. Inverted RCO is the clock for the next stage which is constructed the same as the first stage with the same preload of "0110" but now the inverted RCO has to go back to load on the second stage. This will give you an asyncronous divide by 100
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