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CMOS logic output drive capabilitiy

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BobW

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I've been designing a circuit using CD40xxB logic, the low speed stuff that works with a supply voltage from 3 to 18 volts. According to the CD4011B quad 2-input NAND gate datasheets from both Texas Instruments and Fairchild, when operating on a 5 volt supply, the output drive—both source and sink—is 0.51 mA minimum, and typical is 1 mA (Texas Instruments) or 0.88 mA (Fairchild). But curiously, I'm finding that they can source and sink 8 mA per gate. This is way beyond what the datasheet says they are capable of. I've tried several different ICs, from several manufacturers, and they all behave the same way. So, it seems that the datasheet is ridiculously conservative in the drive ratings.

Looking at the datasheets, they have a rough photocopied look to them, suggesting that they are the originals that date back to when CMOS was first introduced. I'm wondering if, over the years, changes in the fabrication process have improved the chips significantly. But if so, why wouldn't they revise the datasheets?
 
Here's a clip from a 2014 TI document that still shows the relatively low drive capability (**broken link removed** ):
upload_2015-12-3_8-18-54.png


I guess the old stockbroker advice may apply. Individuals results may vary.

John
 
This story is complicated. Sink current:
At 5V supply Vout=0.4V current 1mA typical, 0.51 min and max is ?, (varies greatly with temperature)
At 10V supply Vout=0.5V current 2.6mA typ. 1.3 min ? max
At 15V supply Vout=1.5V current 6.8 2.4, ?
upload_2015-12-3_6-31-12.png

If you allow Vout to be some thing different:
Vout=4V, supply=5V then current typically is 4mA.

So there is (min/typ/max), and (temperature=), and (supply=), and (Vout=) each effect the outcome. Vout could be very high if you are driving a LED not a logic gate.
 
Okay, that makes sense. So essentially, they are saying that if the output voltage isn't allowed to deviate significantly from 0 volts (logic 0), or 5 volts (logic 1), then the current can't exceed about 1 mA. But if the voltage is allowed to droop somewhat, then the current can be significantly higher.
I think I knew this subconsciously. I've powered LEDs from CMOS outputs many times without any problems. It was only when I decided to look at the datasheet, that I was struck by the extremely low current rating.

This all came about because I need to drive a small 5 volt DIP reed relay. It has a 500 ohm coil, so it draws 10 mA. I had planned to use a transistor as a buffer, but since I have several spare CMOS gates, I decided to parallel them to see if they could drive the relay. This worked just fine. And then later, I discovered that it wasn't necessary to parallel the gates. A single gate was able to drive the relay.
 
This all came about because I need to drive a small 5 volt DIP reed relay. It has a 500 ohm coil, so it draws 10 mA...... A single gate was able to drive the relay.
Then you were lucky to find a gate with 10mA of output current at about a 2V loss instead of the 3.5mA shown on the "typical" graph. I assume the relay needs a minimum of 3V for it to work.

Edited the math
 
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A single gate was able to drive the relay.

Maybe, but there are other factors. CMOS outputs basically are more like current sources than voltage sources, so they naturally sum into a common load with better distribution among multiple drivers compared to doing the same thing with TTL gates. Because of this, using multiple gates in parallel not only gets you a lower or higher out voltage, it also spreads the internal driving transistor heat over a larger portion of the chip, directly increasing long-term reliability. Because no two gates transition at exactly the same input voltage or have exactly thee same propagation delay, there is a very short time period (nanoseconds) when the paralleled outputs are fighting each other and trying to short out the power supply. Because of this, real high reliability design rules forbid direct paralleling of gate outputs. But if you're not designing something to fly in space for 20 years and then send back photos of Pluto, you're good to go.

ak
 
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Since 4 Cmos gates or 6 Cmos inverters are fabricated on the same monolithic chip then I think the switching voltage threshold is nearly the same for them.
 
CMOS output basically are more like current sources than voltage sources
I think the 40xx series has outputs that are more like resistors. (Rds-on of a MOSFET) 400 ohms closed and 20meg ohm open +/-
So if a single output is about 400 ohms then paralleling two looks like 200 ohms. 4=100 ohms.
 
Since 4 Cmos gates or 6 Cmos inverters are fabricated on the same monolithic chip then I think the switching voltage threshold is nearly the same for them.

Correct, but "nearly the same" does not *guarantee* cross-conduction periods less than 1 ns by design, and is not good enough for the ultra-high-rel arena. The standard fix is a small resistor in series with each output. Not my rules. I see their point, but I don't agree with it for most situations. The rule probably is left over from TTL days when repeated brief cross-conductions could in fact decrease reliability.

ak
 
CD4xxx Cmos inverters are frequently used with cross-conduction as a sort-of linear amplifier and they last forever when their low supply voltage causes a low conduction current. The graph shows a typical current of only 3mA and the max conduction might be 6mA. The datasheet says 100mW max allowed dissipation and here the maximum dissipation might be only 2.5V x 6mA = 15mW.
 
Yeah, I once built a stereo phono preamp out of a CMOS hex inverter as an experiment.

ak
 
Yeah, I once built a stereo phono preamp out of a CMOS hex inverter as an experiment.
I think it would have very high distortion and cut high audio frequencies if its gain is high. Here is an old test:
 

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Thanks everyone for your comments.

Just to clarify, I'm actually running my circuit from a 6 volt power supply, but I was using the 5 volt specs from the datasheet, since they are closest to my supply voltage.

I went back and rechecked my measurements. With a six volt supply, and driving the relay with two gates in parallel, the relay coil draws 9.75 mA, and the voltage across the coil is 4.85 volts. So the gates are dropping 1.15 volts. That means that two gates in parallel have a resistance of 118 ohms. Hence, a single gate would be 236 ohms. Using a single gate, the current draw would then be 6/(236+500)=8.15 mA, which is what I had measured earlier. This would give a voltage on the coil of 4 volts which is still enough to pull in the relay. The relay is a Littelfuse/Hamlin HE721A0500. According to the relay datasheet, its minimum pull-in voltage is 3.75 volts.

So, these numbers definitely support the position that the CMOS outputs are resistive, and not current sources.

As mentioned earlier, I tested this circuit with chips from different manufacturers, including some very old stock dating back more than 30 years, both 4011 and 74C00 chips. They all behaved exactly the same. So, I have to assume that these are typical characteristics, and not some anomaly related to a single off-spec chip.

I'm not sure whether I'll use a relay in the final circuit. I may end up using a MOSFET to switch the load, as long as I can find one with extremely low off state leakage.
 
So, these numbers definitely support the position that the CMOS outputs are resistive, and not current sources.
See the graph a few posts above? It shows curved lines. A current source is a horizontal straight line and a resistor is a diagonal straight line. The Mosfet curved line is almost a diagonal straight line when the current is low and is almost a horizontal straight line when the current is high. A lousy current source but not a resistor.
 
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