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CMOS gate Input Voltage

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thecritic

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The datasheet of 4069 says this:
At supply voltage (Vdd) of 5 Volts
Input High Voltage --> Minimum 4volts.
Input Low Voltage --> maximum 1 Volts.

How does it Treat voltages in-between. What If I slowly rise the voltage from 0 volts to 5 volts?
 
It will act like a poor inverting amplifier with a gain of about ~25 when the input is at the voltage that causes the output to be near Vdd/2.
 
Gain of -25? If I input 1.5 Volts the output will be -37.5V ? :(
I wanted to know that if i connect a led to the output and slowly increase the input voltage from 0 to 5 (By using RC circuit), would the led sharply switch states or there would be intermediate states?
 
Gain of -25? If I input 1.5 Volts the output will be -37.5V ? :(
I wanted to know that if i connect a led to the output and slowly increase the input voltage from 0 to 5 (By using RC circuit), would the led sharply switch states or there would be intermediate states?

No! Say that to get 2.5 at the output pin, it takes 2.000V at the input. Now move the input voltage to 2.010, a 10mV delta. The output will move from 2.5V to 2.25V, a -250mV delta. Obviously, the output pin cannot be driven above Vdd or below Vss (Gnd).

For all practical purposes, the LED at the output will be either ON or OFF, with very little time as the output slews through the intermediate state.
 
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There is always the possibility of output oscillations around the midpoint of the input voltage due to stray feedback from the output to the input, which is amplified by the gate's gain that MikeML mentioned. If that happens your LED may appear to light at less than full brightness. To avoid this you can use a Schmitt Trigger gate such as the 40106. Such a gate has a distinct input voltage difference between the high and low output states (sort of a snap action), and thus will not oscillate from any stray coupling.
 
There is always the possibility of output oscillations around the midpoint of the input voltage due to stray feedback from the output to the input, which is amplified by the gate's gain that MikeML mentioned.
The CD4069 is a logic inverter. Stray feedback from output to input is negative feedback that simply reduces the high frequency gain and it will not oscillate.
 
So, I think I quite got it. When Input is 1 Volts output is 5 volts. (as the datasheet says).
When input is 1.1 Volts the output is 5 - 25*0.1 = 2.5 Volts (as you said), and when input is 1.2 volts the output is 0 volts. Beyond this the amplifier has already saturated so the output remains 0 volts.
So, the state switching occurs at about 1.2 volts when increasing voltage from 0 to 5.
But, when I decrease voltage from 5 to 0, the stage switching occurs at about 3.8 Volts (by following similar analysis).
If these are true, then isn't the input behaving like Schmitt input?
 
So, I think I quite got it. When Input is 1 Volts output is 5 volts. (as the datasheet says).
When input is 1.1 Volts the output is 5 - 25*0.1 = 2.5 Volts (as you said), and when input is 1.2 volts the output is 0 volts. Beyond this the amplifier has already saturated so the output remains 0 volts.
So, the state switching occurs at about 1.2 volts when increasing voltage from 0 to 5.
But, when I decrease voltage from 5 to 0, the stage switching occurs at about 3.8 Volts (by following similar analysis).
If these are true, then isn't the input behaving like Schmitt input?
Not quite. A Schmitt trigger actually has a small amount of positive feedback which causes the output to abruptly change state at the switch point. This is no point where the output is at any voltage other then 0V or +5V.
 
The CD4069 is a logic inverter. Stray feedback from output to input is negative feedback that simply reduces the high frequency gain and it will not oscillate.
You are correct, of course. Forgot about it being an inverter.

So then the only thing that would cause the output to not switch smoothly is any noise in the input signal which would be amplified during the transition.
 
What you are concerned about on a slow rising edge is noise on the signal can cause false triggers or double clocking. See attached.

**broken link removed**
 
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The Mosfets in a CD4069 inverters IC are symmetrical so it switches when the input is typically at half the supply voltage.
 
Sorry but I am still not altogether clear. Was my analysis at post #6 (excluding the claim of similarity of Schmitt input) correct?
Mikebits Diagram shows that the state switching occurs at around 2.5 volts when increasing from 0 to 5 volts. Is the case same if I decrease from 5 to 0 volts?
In any case, why is the output high even when input is say 1.8 volts (but the datasheet says maximum low level input voltage = 1 volts)

I am sorry if I am repeating something.
Thanks for all the help so far.
 
The CD4069 ICs are not all the same. Some have a stronger P-channel Mosfet and others have a stronger N-channel mosfet. Typical ones have Mosfets with symmetrical strengths so they switch at half the supply voltage. Some switch at 1V and others switch at 4V when the supply is 5V. Some have a switching input voltage that is anywhere between 1V and 4V.

They are a simple linear class-A push-pull amplifier. I have a graph that shows the typical voltage gain is 100 (40dB) with a 5V supply when the output voltage averages at half the supply. The gain drops when the output approaches the positive supply or ground. Since they are a linear amplifier then they do not have the hysteresis of a Schmitt trigger.

If yours has a +5.0V supply and since its output is high when the input is +1.8V then its input switching voltage is above 1.8V which is normal.
 
Thanks. It seems clear now. The ICs switch anywhere between 1 volts and 4 volts which is same whether you decrease from 5 to 0 or increase from 0 to 5;
Even the IC makers don't know this switching voltage, so to be safe they say: Minimum High level input voltage = 4 volts (although 3.5 volts would also work)
 
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