To be honest, I am a newbie to electronic circuits design.
Isn't it easy to implement such divide-by-odd number circuit, like isn't it basic stuff for advanced guys? I mean I did some searching and all I got was an implementation for divide by 3. So guys please help!
I am allowed to use jk or d-triggers, and all simple logic element, like "not" ,"or", "and" and others
Clue:
As 3,5,7,11,13 are primes numbers, you need to include the original clk i.e clk/1 or NOT clk into the combinational logic somewhere. It can be done, but takes a bit of time and thinking.
the thing is I am not in position to understand clues right now, I am asking either for a solution or a complete description theory. I did say I am a newbie)
No it doesn't. The clue is bogus. I can draw you a synchronous state machine that has exactly three states having two flip flops. The input clock goes only to the two clock inputs on the flops. The carry out (which is a signal at 1/3 the frequency of the input clock) can be a decode of only the Q's of the two flops.
Clock frequency divider by 3, 5, 7, 11, 13 is nothing but a binary up-counter that resets when it reaches a count of 2, 4, 6, 10, 12. respectively. Do you know how to build a counter?
true but looking up datasheet and seeing how some product works is not going to do any harm.
besides, the idea is what counts - use counter and select decode output to generate reset.
same can be done with few ICs using basic FFs and gates, for example pair of 74LS74 or 74LS76 as counter
and gates like 74LS13 or 74LS20...