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Capacitive coupling between the gate and the drain/source of a FET (IXTF03N400)

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tweiers

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My problem is related to the capacitve coupling between the gate and the drain of the IXT03N400 FET that I am using as a switch. Whenever I apply 12 V to the gate of my FET, the voltages at the drain first goes up. This increase in voltage is visible as a positive spike on my oscilloscope. After that spike the voltage between drain and source collapses as the n-channel FET becomes conductive.

I am trying to develop an application where I need to switch voltages between 1.7 V and 300 V within a maximum of 60 ns. In other words, I apply 12 V at the gate in order to switch voltages between 1.7 V and 300 V. The voltage is supplied by a commercially available flyback converter (Traco MHV).

Those positive voltage spikes at the drain electrode of my FET are unacceptable within the context of my application. Any idea of how I can ressolve this issue?
 

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What are you really trying to do?
What is the purpose of the 0.8pF cap?
What is the significance of 1.7V?
How much current can the 300V supply?
How wide is the pulse on the gate of the MOSFET?
What is the frequency?
You may think I'm nosy, but the questions are relevant to solving your problem.
 
Good day Ron,

I am building a device that injects electric charge between 1 pC and 100 pC through a 0.8 pF capacitor.
The maximum current from the Traco MHV 300 V supply is 10 mA.
The MOSFET is fast, td(on) is 17 ns, tr is 16 ns. I have attached the datasheet (FET_IXTF03N400.pdf).

Actually, the problem of capacitive coupling between gate and drain seems worst when the voltage between source and drain is below 10 V. The capactive coupling then results in these nasty spikes of positive voltage on the drain electrode.
 

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Integrated-circuit Analog multiplexers solve your problem by having both a Pfet and Nfet connected in parallel to create the switch. The gates are driven with equal but opposite-polarity gate signals, so the capacitive feed-through is mostly canceled out. In VLSI design, its all about symmetry in the layout of the analog switch cell.
 
Integrated-circuit Analog multiplexers solve your problem by having both a Pfet and Nfet connected in parallel to create the switch. The gates are driven with equal but opposite-polarity gate signals, so the capacitive feed-through is mostly canceled out. In VLSI design, its all about symmetry in the layout of the analog switch cell.
But they won't handle 300V.
 
What does the 0.8pF capacitor actully consist of, or represent?

You only answered a couple of my previous questions.
 
Supertex transistors and capacitors

Thank you, Ron, for your hint about the Supertex transistors. They seem, however, hard to buy. At least Digikey doesn't have the TN2540N3 model that I am after.

That is why I have requested samples directly from Supertex.

As for the 0.8 pF capacitor, any capacitor < 1 pF and capapble of withstanding 300 V will do. At present, I am experimenting with voltages < 50 V, so a standard ceramic capacitor does the job.
 
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