LIST
; P12F509.INC STANDARD HEADER FILE, VERSION 1.00 MICROCHIP TECHNOLOGY, INC.
NOLIST
IFNDEF __12F509
MESSG "PROCESSOR-HEADER FILE MISMATCH. VERIFY SELECTED PROCESSOR."
ENDIF
;==========================================================================
;
; REGISTER DEFINITIONS
;
;==========================================================================
W EQU H'0000'
F EQU H'0001'
;----- REGISTER FILES -----------------------------------------------------
INDF EQU H'0000'
TMR0 EQU H'0001'
PCL EQU H'0002'
STATUS EQU H'0003'
FSR EQU H'0004'
OSCCAL EQU H'0005'
GPIO EQU H'0006'
;----- STATUS BITS --------------------------------------------------------
GPWUF EQU H'0007'
PA0 EQU H'0005'
NOT_TO EQU H'0004'
NOT_PD EQU H'0003'
Z EQU H'0002'
DC EQU H'0001'
C EQU H'0000'
;----- OPTION BITS --------------------------------------------------------
NOT_GPWU EQU H'0007'
NOT_GPPU EQU H'0006'
T0CS EQU H'0005'
T0SE EQU H'0004'
PSA EQU H'0003'
PS2 EQU H'0002'
PS1 EQU H'0001'
PS0 EQU H'0000'
;----- OSCCAL BITS --------------------------------------------------------
CAL6 EQU H'0007'
CAL5 EQU H'0006'
CAL4 EQU H'0005'
CAL3 EQU H'0004'
CAL2 EQU H'0003'
CAL1 EQU H'0002'
CAL0 EQU H'0001'
;==========================================================================
;
; RAM DEFINITION
;
;==========================================================================
__MAXRAM H'3F'
;==========================================================================
;
; CONFIGURATION BITS
;
;==========================================================================
_MCLRE_ON EQU H'0FFF'
_MCLRE_OFF EQU H'0FEF'
_CP_ON EQU H'0FF7'
_CP_OFF EQU H'0FFF'
_WDT_ON EQU H'0FFF'
_WDT_OFF EQU H'0FFB'
_LP_OSC EQU H'0FFC'
_XT_OSC EQU H'0FFD'
_INTRC_OSC EQU H'0FFE'
_EXTRC_OSC EQU H'0FFF'
LIST
__CONFIG _WDT_ON & _INTRC_OSC & _MCLRE_ON & _CP_OFF
#DEFINE BUZZ GPIO,1
;BUZZ EQU GPIO,1 ;PIEZO BUZZER PIN
;LDR EQU PORTB.0 ;LDR/CAP PIN
#DEFINE LDR GPIO,0
;VARIABLES UDATA
COUNT EQU 0X0A ;HOW MANY HIGHS WHEN CAP IS DISCHARGING
DCOUNT EQU 0X08 ;DELAY COUNTER
LCOUNT EQU 0X09 ;LOOP COUNTER TO READ LDR
TOP
MOVLW B'00000000' ;SET BUZZER AND LDR AS OUTPUT
TRIS GPIO
BCF LDR ;GROUND OUT LDR/CAP
CALL DELAY ;LET CAP CHARGE
MOVLW B'00000001' ;FLIP LDR FOR INPUT
TRIS GPIO
CLRF COUNT ;ZERO COUNTERS, COUNT = NUMBER OF HIGHS FROM RC, LCOUNT IS PASSES TO CHECK
CLRF LCOUNT
LOOP
BTFSC LDR ;IF BIT IS HIGH
INCF COUNT,F ; INCREMENT COUNT
DECFSZ LCOUNT,F ;DECREMENT LOOP COUNTER
GOTO LOOP ;IF LOOP COUNTER <> 0 LOOP
BTFSC COUNT,7 ;TEST BIT 7 IF MORE THAN 128 HIGHS
GOTO BUZZ1 ;IF TRUE GO BUZZ
NAP
SLEEP ;ELSE SLEEP WAIT FOR WDT
GOTO TOP
BUZZ1
CLRF LCOUNT
NOISE
BSF BUZZ ;SET PIEZO HIGH
CALL DELAY ;PAUSE
BCF BUZZ ;CLR PIEZO
CALL DELAY ;PAUSE
DECFSZ LCOUNT,F ;IF LCOUNT IS <> 0
GOTO NOISE ;THEN MORE NOISE
GOTO NAP ;ELSE TO NAP
DELAY CLRF DCOUNT
DELAY1
DECFSZ DCOUNT,F
GOTO DELAY1
RETLW .0
END