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AVR based logic analyzer.

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ikalogic

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Hello,

I've been working from a couple of weeks on building a logic analyzer using an ATMEGA16 microcontroller.

my fist goal is to make a 4 channel, 1MHz sampling rate analyzer. Future development are on the way.

The connectivity to the PC would be via RS232 (or USB via a USB to RS232 cable)

The PC will have a Visual basic program to receive all data an draw it.

My goal is also to make the visual basic program capable of decoding UART, SPI, I2C, and CAN buses.

I have already solved the PC to ATMEGA16 connectivity problem. I have also found a *new* idea to auto-correct the timebase of the ATM EGA based on the RS232 clock..

I have successfully coded the inline ASSEMBLY codes for 1MHz sampling.

Sooner or later i should start on with the hardware implementation.

My question: are people here interested in such a project? I am planing to take lot of pictures during the building of the project, and make the software available for download with documentation. That will be a lot of work, and i'll be happy to do it, if i feel that it of some interest to you.

Is it?

I also hope there will some active participation and suggestions from fellow members, which is logical considered such a project/software will be interesting for the electronics and robotics community.

Waiting for your comments.

Regards.
 
anyway.. i feel like the community here - to my surprise - is not very motivated about such a project...
 
blueroomelectronics said:
The PICkit2 has a builtin 3 channel 1mhz logic analyzer built in to the software. USB too.

Well, i am building it anyway, and i love AVR and ATMEL! every one got his fans!

lol, anyway, i wanted to ask, is 1MHz logic analyser means that it can sample clearly signals at 1Mhz, or that it takes 1 Million samples per second?
 
I think it sounds great Ika

I've played around with VB quite a bit with regards to UART, but not with USB unfortunately..

If you keep it simple, then the raw programming of the micro will be minimal, especially if you use UART

The Logic Analyzer;

Monitor the status of the Pin and when it changes send a byte through UART with the relevant information (high/low). The VB program will display a running image with the data with its refresh rate (time scale) being changeable by the user.

The time it takes to send one byte via UART will be your smallest resolution. Its crude, but it will work for a simple logic analyzer, and will get decent speeds with a fast enough UART.


The Oscilloscope;

This will require bi directional UART, primarily for setting the time scale. Create a routine that waits for a positive zero crossover, and then grabs 256 samples and stores the data into an array.

The time between samples could be extended with NOP's or by burning cycles (as required by the user on the VB side of things). Send the 256 bytes of data to the PC, for display on the VB program. It simply maps the 256 ADC values on a graph and waits for the next signal.


Your thoughts?




Sorry about your post on my site BTW, I used Web Expressions to update the site instead of a standard ftp program, problem is, it deleted all folders that were not found locally on the computer - the forum being one of them.
 
I'm not at my computer but I recall it alises @ 500kHz. Handy tool either way, plus a UART tool too. Not too shabby for an inexpensive programmer / debugger.
 
ikalogic said:
Well, i am building it anyway, and i love AVR and ATMEL! every one got his fans!

lol, anyway, i wanted to ask, is 1MHz logic analyzer means that it can sample clearly signals at 1Mhz, or that it takes 1 Million samples per second?

You can take a sample every 1/1000000 of a second. Say your display contained 64 co-ords for displaying the captured data, this means that 1/(1/1000000 * 64) is the fastest sine wave you can sample, this of course limits the max frequency it can sample too 15.625 KHz

You can go faster, but you will not be able to sample the complete sinusoidal signal, or decrease the resolution of the result

Zero crossover detection is simple,
Code:
While True
    // ensure the signal is below zero crossover
    Repeat
    Until Adin(0) <= 511

    // wait for the signal to go positive above zero crossover
    Repeat
    Until Adin(0) >= 511

    // take samples
    Sample = 0
    For Sample = 0 to 64
        ADCSample(Sample) = Adin(0)
        DelayuS(TimeScaleFactor)
    Next
    
    // write data to UART
    USART.Write("New Sample")
    Sample = 0
    For Sample = 0 to 64
        USART.Write(Convert.DecToStr(ADCSample(Sample))
    Next

Wend

Thats almost my whole OSC program, but I can't find the origianls since re-installed windows. Both the Delay and Adin modules were modified to provide application specific speeds/delays
 
gramo said:
I think it sounds great Ika

The time it takes to send one byte via UART will be your smallest resolution. Its crude, but it will work for a simple logic analyzer, and will get decent speeds with a fast enough UART.

Well, the interesting part of my project it that i wont rely on the speed of UART to transfer the states of the 4 channels... i will store them immediately on the micro controller (i could store up to 2000 samples per channel), while still leaving like 500 bytes of free memory for my program variables. then they would be sent to the PC. A trigger signal would initiate the sampling cycle (it could be rizing/falling edge, etc..)

I however intend to give the user the possibility of "free running" analyzer, where the 4 channels will arrive at the same speed of the UART, this mode will allow the user to see the channels live, but won't be optimized for speed..

gramo, i have a question, with 1 MHz sampling rate, what is the maximum frequency of the signal that can be analyzed clearly.. if you see what i mean?
In other words, how much higher the sampling frequency has to be than the measured signal frequency for acceptable results?

and about the OSC, thanks but i really want to stick to the logic analyzer for now.. one thing at a time! but thanks anyway :)
 
ikalogic said:
I however intend to give the user the possibility of "free running" analyzer, where the 4 channels will arrive at the same speed of the UART, this mode will allow the user to see the channels live, but won't be optimized for speed..


This will suite most applications given the target audience I'd imagine

ikalogic said:
gramo, i have a question, with 1 MHz sampling rate, what is the maximum frequency of the signal that can be analyzed clearly.. if you see what i mean?
In other words, how much higher the sampling frequency has to be than the measured signal frequency for acceptable results?

Seems we are posting in and around ourselves :eek: I posted an example earlier, but also forgot to mention that the impedance of the sample will be a factor given the time it takes to charge/discharge the internal capacitors on the micro side of things. For most applications this isn't and issue, but for some high frequency, and high impedance samples, there results will not be 1:1


ikalogic said:
and about the OSC, thanks but i really want to stick to the logic analyzer for now.. one thing at a time! but thanks anyway :)


Nps, just putting it out there for you :eek:
 
ikalogic said:
In other words, how much higher the sampling frequency has to be than the measured signal frequency for acceptable results?


Sorry, I didn't explain that bit, I came from the oscilloscope perspective working with the frequency of a sinusoidal wave.

Your resolution will be limited by the code overhead of the samples for the logic analyzer, from there you can calculate the error/max frequencies attainable
 
Let me put it this way:

i allready managed to write the code to achieve 1MS/s.

What is the max frequency of the signal that can be sampled? 2.5 times less as some websites say, although i am skeptic..? or what?

thanks for your enlightening!
 
ikalogic said:
What is the max frequency of the signal that can be sampled? 2.5 times less as some websites say, although i am skeptic..? or what?

Besides frequency, things just don't all happen at the same time.

Ask yourself this simple question:

If there are two logic levels changing one after another, will my sampling frequency will be fast enough to catch and distinguish them?

E.g. You have two 1KHz square signals. The rising edge of the second one lags the first one by 100ns. Will the sampling results tell them apart? What if they differs by 500ns or even 1us?
 
The LAs I worked with had two modes. Sort of like sync and async.

The first is logic mode (may be another name) where you only need to know the state for each clock period. This mode is most often used in well behaved systems like a computer bus.

The second is timing mode. This works much like a scope except data is recorded as a logic state instead of an analog value. The requires a much higher sample rate.

I think Erick is talking about timing mode. This makes sense since there is little use for a 4 bit LA in logic mode.

Edit: looks like I have the names switched.
 
Last edited:
I had an idea to build a small and inexpensive but much more powerful (100 MHz sample rate) L.A. using a small FPGA - Spartan 3E-100, costs less than $10 at DigiKey.com, USB connectivity would be provided with PIC18F2455 USB PIC micro. The HW was really simple - the main circuit contained (not counting the power supply) just 2 ICs - the FPGA and the PIC micro (which would initialize the FPGA with a configuration file downloaded from the PC). The design could be upgraded with a fast external SRAM (one additional IC).

In the end I did not do this because I was lazy to do the PCB layout - I hate doing layout for big fine-pitch QFP packages (the FPGA is VQFP-100 with 0.5 mm pitch).

Later I needed a L.A. urgently so I had to buy one - I have bought the one from INTRONIX (https://www.pctestinstruments.com/) - for almost $400 it was a big investment (for a hobbyist) but it is really an excellent tool.

So the FPGA and other components are waiting in my drawer until I find another use for them :)
 
eblc1388 said:
Besides frequency, things just don't all happen at the same time.

Ask yourself this simple question:

If there are two logic levels changing one after another, will my sampling frequency will be fast enough to catch and distinguish them?

E.g. You have two 1KHz square signals. The rising edge of the second one lags the first one by 100ns. Will the sampling results tell them apart? What if they differs by 500ns or even 1us?

Ok, that means that a 1 MHz sampling rate give me a 1 uS resolution, any change faster than than that could be *not* in the time it really changed, but at the nearest sampling point.

right?
 
That's about right.

Nevertheless, a 1MHz sampling rate is often good enough for 95% of applications one would encounter, especially events like I/O port levels that are clocked and will change only synchronously to a common system clock.

Your main challenge in a project of this kind is writing the PC host software which would read the collected data and display them, zooming in/out, triggering and user selectable timing cursors for measurement.
 
Last edited:
eblc1388 said:
That's about right.

Nevertheless, a 1MHz sampling rate is often good enough for 95% of applications one would encounter, especially events like I/O port levels that are clocked and will change only synchronously to a common system clock.

Your main challenge in a project of this kind is writing the PC host software which would read the collected data and display them, zooming in/out, triggering and user selectable timing cursors for measurement.

Okay then! That's exactly what i was thinking also. thanks for backing me up!

now about the PC software, i'm an 'old' visual basic programmer (before even i touch uCs) so it should be fun for me to get back all those memories.. back then, i've made some complicated 3D drawing programs, image converters, and simple RPGs, this should help me along my journey!
 
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