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Automatic Gain Control design

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electroRF

Member
Hi,
I'm trying to understand the following design of an AGC unit.

This AGC unit forms a CLPC from the PA's output to the PA's BIAS network,
and its duty is to control the BIAS network of the PA in order to maintain a desired output power of the PA.
The PA's input signal frequency is 10MHz.

The AGC receives:
- vin - Output voltage of PA.
- vset - DC Control signal that represents desired output power level of the PA.

and the AGC outputs:
- vapc - Control Signal that goes to the BIAS network of the PA.

View attachment 65279

I'll be happy to receive your inputs about this design.

I believe that vctl should be a DC voltage, that represents the PA's output voltage, but instead I get a "dirty" signal.

Thank you very much for any help!
 
Hi electroRF,

you speak about an automatic gain control circuitry - however, I cannot see any control loop. Where does the voltage Vctl comes from?
W.
 
I believe that vctl should be a DC voltage, that represents the PA's output voltage, but instead I get a "dirty" signal.

Yes, the control voltage Vctl should be a dc signal derived from the PA output - and what is your problem now? What means "dirty"?
Are you speaking about measurement or simulation?

W.
 

electroRF

Member
I believe that vctl should be a DC voltage, that represents the PA's output voltage, but instead I get a "dirty" signal.

Yes, the control voltage Vctl should be a dc signal derived from the PA output - and what is your problem now? What means "dirty"?
Are you speaking about measurement or simulation?

W.

Hi.
I simulated the circuit, using Transient simulation.
Start time: 5usec
Stop Time: 15usec
Step size: 1nsec

Results:
Vin
View attachment 65290

Vcoupler
View attachment 65291

Vdet
View attachment 65292

Vctl - "dirty signal"
View attachment 65293

Vset = 3V DC
View attachment 65296

Vplus - I do not understand why it is not a clean DC voltage
View attachment 65297

Vapc0
View attachment 65294

Vapc
View attachment 65295
 
Where is in your block diagram Vplus?
When the control signal is "dirty" it contains to much from the PA output signal due to bad filtering after detection.

Added some minutes later : OK, I have found Vplus. It is just a shifted version of Vctl.
 
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electroRF

Member
Where is in your block diagram Vplus?
When the control signal is "dirty" it contains to much from the PA output signal due to bad filtering after detection.

Added some minutes later : OK, I have found Vplus. It is just a shifted version of Vctl.

Hi,
Thank you again Winterstone!

Can you please elaborate on why Vctl and Vplus aren't clean DC signals?
How can it be worked out?

Thank you very much!

--Edit
Vplus is actually formed by a voltage divider between Vset and 1.5V DC signal.
 
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RCinFLA

Well-Known Member
The circuit is the dc control for an RF PA. The "vcoupler" is the RF output sampled from a directional coupler put in series with PA out to sample some of the forward power. The directional coupler loss is typically selected to be 10 db to 20 db down from the forward power of the PA.

The first two stages in the simulation form an RF to a log detector producing a DC voltage output proportional to db weighting of RF input, like an Analog Devices AD8319. This detector has a low frequency pole within its RF to DC conversion so it must be part of the loop analysis. The DC output from the log detector is then run into the two op amp low pass filter amps. The 'vset' input makes a variable DC offset on the first op amp. Its purpose is to set the desired PA RF output level. The loop then is suppose to make fine adjustments to maintain a regulated output RF power from the PA.

The whole system is a feedback control loop. To do any loop stability analysis you need the PA's gain control response. First is the plot of its Vcontrol input to RF power output. The PA is likely not a straight linear power output for voltage control point setting. All this has the potential to make the loop unstable at some point in the power setting level. The low pass filters made with the op amp job is to slow the feedback response to keep the closed loop stable.

You may find several explainations of the power control loop systems by referring to RF PA manufacturers data sheet and/or the log detector circuit IC by its manufacturers'. (Analog Devices, Maxim, Skyworks, Avago, Anadigics and TriQuint just to name a few)

The whole DC path seems to have a lot of gain which can cause instability. Your Vdet output does not look like it should. You can plots its RF input to DC output as an isolated entity. Also, realize the loop response is likely very slow in relation to your simulation time. Initial conditions must be given some time to stabilize from initial transient simulation startup. The typical issue with these loops is caused by the PA's Vcontrol to RF level has a changing gain slope depending on what power level is set. This makes the loop gain vary over power settings. The worse stability point is where the PA's Vcontrol to RF output has the highest gain slope.
 
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Hi electroRF,

I think, RCinFLA has given you a very good and detailed description of the whole system.
In this context, he also has mentioned loop stability which is, of course, a very important aspect that deserves some specific investigations.
However, as far as the "dirty" signal is concerned, I think - as already mentioned in my previuos post - it is simply a result of bad filtering after signal detection.

Why are you surprised? Why do you expect a clean dc signal representing the output power?
There is no signal detection process that really can give you a "clean" and undistorted dc signal because each filter can provide for unwanted frequency components a finite attenuation only.
And - in your case - it seems that the filter is badly designed or you must select a higher filter order.
Therefore my question: Is the frequency of the "dirty" components identical to the output frequency?

W.
 

electroRF

Member
I deeply thank you :)

I'm following your comments step by step to understand the entire loop.

The whole DC path seems to have a lot of gain which can cause instability. Your Vdet output does not look like it should. You can plots its RF input to DC output as an isolated entity.


I followed your instruction, and entered a 1V amplitude @ 10MHz AC signal into the log detector.
I put on a graph Vout Vs Vin.

View attachment 65318

View attachment 65319

As can be seen, Vout is not DC.
Would you expect it to be DC?
 
ElectroRF,

I repeat my recommendation to compare the frequencies of the output signal and the "dirty" components, respectively.
This can give you a clear indication if it is a filtering or a stability problem.

W.
 

RCinFLA

Well-Known Member
You already have three dominate poles associated with the control loop. First pole is caused by the PA bias bypass capacitors, second is the RF detector filter, and third is the cap across feedback resistor in last op amp. This is hard to keep stable when there is a wide variance in loop gain across the power level settings caused by the PA Vcontrol to RF power gain slope.

Your first most appearent problem is the detector. You did not mention the frequency of PA but you have to be sure the filter on the detector is appropriate for the RF frequency rectification and filtering. You can't put in a circuit with a detection filter designed for 900 MHz and inject a 1 MHz RF frequency in the simulation and expect not to get RF ripple feedthru on the detector output which is what your simulation appears to have. Just look at the first two stages. Inject various fixed RF levels and check DC level out of detector. It should be pure DC voltage with no AC ripple from RF input frequency.

If SDD2P is just a math block that looks like a simple log rectifier then you need a filter on its output to remove the RF ripple. That may be what R'2-C1 is for in your original circuit (vctl point). Look at the detector output at that point. It should be pure DC for fixed RF input level. Increase C1 value to clean up RF ripple. Try setting 1/(2pi * R'2C1) to be less then 100 kHz.

Your loop response for a 10 MHz PA is going to have to be slow, in order of milliseconds.
 
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